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參數(shù)資料
| 型號： | MC68838FCC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 24/100頁 |
| 文件大?。?/td> | 465K |
| 代理商： | MC68838FCC |
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MOTOROLA
MC68838 USER’S MANUAL
iii
TABLE OF CONTENTS
Paragraph
Page
Number
Title
Number
Section 1
Introduction
1.1
Overview...........................................................................................................1-2
1.2
Chip Features..................................................................................................1-2
Section 2
Functional Description
2.1
Node Processor Interface Logic...................................................................2-1
2.2
Receive Data Path..........................................................................................2-1
2.2.1
Receive Latch..............................................................................................2-2
2.2.2
Receive CRC Checker...............................................................................2-3
2.2.3
Sent Count...................................................................................................2-3
2.2.4
Counters.......................................................................................................2-3
2.2.5
Receive Finite State Machine...................................................................2-3
2.2.6
Address Comparator..................................................................................2-4
2.2.7
Receive Host Interface...............................................................................2-4
2.3
Transmit Data Path.........................................................................................2-4
2.3.1
Transmit Data Host lnterface ....................................................................2-5
2.3.2
Send Frame Logic......................................................................................2-5
2.3.3
Capture Token Logic..................................................................................2-5
2.3.4
Transmit CRC Generator...........................................................................2-6
2.3.5
Transmit Finite State Machine..................................................................2-6
2.3.6
Timers ...........................................................................................................2-6
2.3.7
Transmit Data Latch (and Repeat Function)..........................................2-7
2.4
Test and Clock Logic......................................................................................2-7
Section 3
Register Description
3.1
Register Types.................................................................................................3-3
3.1.1
Read/Write Registers..................................................................................3-3
3.1.2
Read/Control Write Registers ...................................................................3-3
3.1.3
Read-Only/Clear Registers .......................................................................3-3
3.1.4
Read-Only Registers ..................................................................................3-3
3.2
Control and Status Registers........................................................................3-4
3.2.1
Control Register A (MAC_CNTRL_A) .....................................................3-4
3.2.2
Control Register B (MAC_CNTRL_B) .....................................................3-8
ARCHIVE
INFORMA
TION
ARCHIVE
INFORMA
TION
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