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參數(shù)資料
| 型號： | MC68838FCC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 52/100頁 |
| 文件大小： | 465K |
| 代理商： | MC68838FCC |
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4- 2
MC68838 USER’S MANUAL
MOTOROLA
NP Clock (NPCLK)
This TTL-level input signal is used to run the NPI logic on the chip. It is normally
externally tied to the BYTCLK pin; it is provided separately only for chip testing. For full-
speed operation, NPCLK and BYTCLK must be tied together.
Symbol Clock (SYMCLK)
This TTL-level input signal is used to generate the internal SAMPLE_CLK, which is
used to sample and hold certain MAC chip inputs until a subsequent rising edge of
BYTCLK comes along. This is used to prevent hold time problems between the various
chips, caused (in part) because of clock skew between BYTCLK on the various chips.
SAMPLE_CLK is derived by using the falling edge of SYMCLK to sample BYTCLK,
producing a signal which looks just like BYTCLK except that it lags BYTCLK by about
20 ns. The falling edge of SAMPLE_CLK is what actually latches and holds the input
signals. All the ELM chip and RMC chip inputs to the MAC are sampled and held in this
manner, specifically, the RCDAT bus, the TPATH bus, the TXCTL bus, the TPRITY
signal, and the RABORT signal.
Power-Up Reset (
PWRUP)
This TTL-level input signal is used for power-up reset of the chip. For power-up reset to
work properly,
PWRUP must be asserted low for at least two cycles of BYTCLK,
followed by at least eight or more cycles of BYTCLK during which
PWRUP can be either
asserted or negated. This pin is then negated to allow the chip to be tested or placed
into operation. This pin can also be asserted at any time during normal operation of the
chip, in which case all state information and parameters are lost. The assertion and
negation of
PWRUP can be asynchronous. MACSEL should be negated when PWRUP
is negated.
4.2 NODE PROCESSOR INTERFACE
All NPI signals are synchronous to NPCLK. During normal operation, this clock is the
same as BYTCLK. The two clocks may be separated for the purpose of diagnostics and
testing.
MAC Select (
MACSEL)
This TTL-level input signal indicates to the MAC whether the NP wishes to perform a
register read or write (
MACSEL is asserted (low)). When MACSEL is negated (high), the
MAC three-states the NPDx bus, the NPAx bus, and the NPRW line.
MAC Interrupt (
MACINT)
This CMOS-level output signal is used to notify an external processor of the occurrence
of some event. The MAC operates in a nonvector interrupt mode and the NP must read
the appropriate interrupt register to determine the interrupt or interrupts that caused the
event. This output will remain asserted (low) until the appropriate interrupt is read to
clear the interrupting event(s) or the interrupt is masked by writing a zero into the
appropriate interrupt mask register bit.
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