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參數(shù)資料
| 型號： | MC68838FCC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 59/100頁 |
| 文件大?。?/td> | 465K |
| 代理商： | MC68838FCC |
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5-2
MC68838 USER’S MANUAL
MOTOROLA
clock edge, the MAC begins to drive the NPDx bus. The MAC waits at least 40 ns to
allow the chip previously driving the bus time to three-state the bus.
After the next rising edge of the NPCLK (the second rising edge after the assertion of
MACSEL), the data on the NPDx bus is valid. It remains valid until after the second rising
edge of NPCLK after the negation of
MACSEL. The MAC three-states the NPDx bus
within 40 ns after this clock edge.
The timing described allows a read cycle to occur every 160 ns. However, if the NP
needs to extend the cycle and have the NPDx bus valid longer than one clock cycle, it
can delay the negation of
MACSEL (see Figure 5-1). For a minimum-length read cycle,
the NP must negate
MACSEL a setup time before the second rising edge of NPCLK
following the assertion of
MACSEL. If MACSEL remains asserted for a hold time after the
second rising edge of NPCLK, the MAC continues to drive the NPDx bus with valid data
until after the fourth rising edge of NPCLK. The NP can extend the read cycle indefinitely
by maintaining the assertion of
MACSEL.
CS
NPRW
NPA
NPD
BYTCLK (NPCLK)
Figure 5-1. Node Processor Bus Read Cycles
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