參數(shù)資料
型號： MC68838FCC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120
封裝： CERAMIC, QFP-120
文件頁數(shù)： 66/100頁
文件大?。?/td> 465K
代理商： MC68838FCC
MOTOROLA
MC68838 USER’S MANUAL
7-3
end of a token cycle (i.e., the MAC receives a token, a claim, or a beacon frame) tells the
FSI transmitter that it can complete its frame status association process since no further
frame status indicators are expected for packets that have been previously transmitted.
RCCTL2–RCCTL0 are used to interpret the value of the data on the RPATHx bus as
either two data symbols, end of frame status, frame status indicators, or filler.
Normally, the interface goes through the following sequence of transfers:
1. One or more FILLERS
2. One START_DATA
3. Zero or more DATAs
4. One END_DATA
5. One FRAME_STATUS (where the FRAME_STATUS transfer may be preceded by
zero or more FILLERS)
The whole sequence is then repeated for the next frame.
Note that even when there are no frame status symbols or when the MAC is asking the
FSI to discard a frame (i.e., F-bit = 1), there is still a FRAME_STATUS transfer; it may
simply state that there are no FS indicators. FILLER appearing between the last
FRAME_STATUS and the following START_DATA will always have RPATHx = 0;
whereas, FILLER appearing between END_DATA and the following FRAME_STATUS
transfer will have RPATH7 = 1 and RPATH6–RPATH0 = 0.
Possible exceptions to the above sequence can occur when:
1. The MAC chip is turned off via the MAC_ON bit, or
2. The
PWRUP pin is asserted, or
3. A packet ends abruptly with a JK immediately following two data symbols (data
transfer). For this case, the MAC will simply ignore the second frame by generating
a FRAME_STATUS for the first frame, followed by one or more FILLERS,
eventually followed by a START_DATA for the frame following the bad frame that
ended the first frame.
The MAC chip will send FILLER (RPATHx = 0) whenever MAC_ON is zero or
PWRUP is
asserted. Figure 7-1, the receive data flowchart, illustrates the sequence of data and data
types that are impressed on the receive interface.
The frame status bits (the s ssss bits in Table 7-1) contained in the FRAME_STATUS
transfer hold the received frame status, not the repeated frame status. Hence, these bits
are not affected by the E_FLAG, A_FLAG, and C_FLAG or by the register bits SET_BIT_4
and SET_BIT_5 described in Section 3 Registers.
The F-bit on a FRAME_STATUS transfer is usually the same as the F-bit of the preceding
END_DATA transfer. The only time they differ is when this frame is a secondary NSA
frame and the MAC has been programmed to flush such frames. Therefore, the F-bit can
only change from a zero on an END_DATA transfer to a one on a FRAME_STATUS of a
secondary NSA frame.
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