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參數(shù)資料
| 型號： | MC68838FCC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 36/100頁 |
| 文件大?。?/td> | 465K |
| 代理商： | MC68838FCC |
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3- 20
MC68838 USER’S MANUAL
MOTOROLA
matching a CAM entry. This bit is not set if the A indicator is not received or if DA = my
long address register, where my long address register is a group address.
3.3.2 Interrupt Event Register B (INTR_EVENT_B)
15
14
13
12
11
10
9
8
MY_BEACON
OTHER_
BEACON
HIGHER_
CLAIM
LOWER_CLAIM
MY_CLAIM
BAD_T_BID
PURGE_ERR
BRIDGE_
STRIP_ERR
76543210
WON_CLAIM
NP_ERR
SI_ERR
NOT_COPIED
FDX_CHANGE
BIT4_I_SS
BIT5_I_SS
BAD_CRC_
SENT
MY_BEACON—My Beacon
This bit is set when the receiver FSM signals the MY_BEACON event. The conditions
that cause the receiver FSM to signal this condition are described in the ANSI FDDI
MAC standard in the MAC receiver FSM text and state diagram. Although the receiver
only asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt
remains set until it is read by the external processor.
OTHER_BEACON—Other Beacon
This bit is set when the receiver FSM signals the OTHER_BEACON event. The
conditions that cause the receiver FSM to signal this condition are described in the ANSI
FDDI MAC standard in the MAC receiver FSM text and state diagram. Although the
receiver only asserts this signal for one clock cycle, as with all MAC interrupts, this
interrupt remains set until it is read by the external processor.
HIGHER_CLAIM—Higher Claim
This bit is set when the receiver FSM signals the HIGHER_CLAIM event. The conditions
that cause the receiver FSM to signal this condition are described in the ANSI FDDI
MAC standard in the MAC receiver FSM text and state diagram. Although the receiver
only asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt
remains set until it is read by the external processor.
LOWER_CLAIM—Lower Claim
This bit is set when the receiver FSM signals the LOWER_CLAIM event. The conditions
that cause the receiver FSM to signal this condition are described in the ANSI FDDI
MAC standard in the MAC receiver FSM text and state diagram. Although the receiver
only asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt
remains set until it is read by the external processor.
MY_CLAIM—My Claim
This bit is set when the receiver FSM signals the MY_CLAIM event. The conditions that
cause the receiver FSM to signal this condition are described in the ANSI FDDI MAC
standard in the MAC receiver FSM text and state diagram. Although the receiver only
asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt remains
set until it is read by the external processor.
ARCHIVE
INFORMA
TION
ARCHIVE
INFORMA
TION
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