參數(shù)資料
型號(hào)： MC68838FCC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120
封裝： CERAMIC, QFP-120
文件頁(yè)數(shù)： 38/100頁(yè)
文件大?。?/td> 465K
代理商： MC68838FCC
3- 22
MC68838 USER’S MANUAL
MOTOROLA
NOT_COPIED—Addressed Frame Not Copied
This bit is set when a frame is addressed to this station but cannot be copied.
Specifically, this bit is set when:
The receiver FSM signals FR_Received (i.e., FDDI MAC receiver transition R(41f)
or R(40b)) and the A_FLAG is set (i.e., DA matches my short address register, my
long address register, or CAM, or DA is broadcast and DSABL_BRDCST is zero)
and the E_FLAG is cleared (i.e., valid data length and valid CRC or implementor
frame and E-indicator must be an R-symbol) and the C_FLAG is cleared (i.e., FSI
aborted reception via RABORT) and the N_FLAG is cleared (i.e., not a secondary
NSA frame).
Therefore, this bit is never set for secondary NSA frames but can be set for primary NSA
frames.
FDX_CHANGE—FDX Mode Change
Change in FDX mode. This bit is set when the transmitter enters the FDX mode of
operation (i.e., first enters either the FDX_Idle state or FDX_Data state) or when it
leaves FDX mode (i.e., first leaves both of these states but does not go to the off state).
BIT4_I_SS—Bit 4 Indicator S-Symbol Received
The fourth received control indicator is an S-symbol. This bit is set when the fourth
control indicator received is an S-symbol and SET_BIT4 = 1 in control register B.
BIT5_I_SS—Bit 5 Indicator S-Symbol Received
The fifth received control indicator is an S-symbol. This bit is set when the fifth control
indicator received is an S-symbol and SET_BIT5=1 in control register A.
BAD_CRC_SENT—Bad CRC Sent
This bit indicates that a packet with bad CRC has been transmitted. This bit is set when
the transmitter is requested to send a packet without adding an FCS field onto the end
of it (presumably because the CRC has already been computed and added to the end of
the packet), and it detects that the precomputed CRC is incorrect. The transmitter still
sends the packet as if it did not detect a problem. This bit is set even for reserved-for-
implementor frames. On the other hand, this bit is not set if the MAC aborts the
transmission of the frame (i.e., sends a fragment).
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