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參數(shù)資料
| 型號： | MC68838FCC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 54/100頁 |
| 文件大?。?/td> | 465K |
| 代理商： | MC68838FCC |
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4- 4
MC68838 USER’S MANUAL
MOTOROLA
Receive Control Signals (RCCTL4–RCCTL0)
These CMOS-level output signals are used to indicate the type of FSI transfer
presented on the RPATHx bus. These signals are synchronous to BYTCLK and
RPATHx. A detailed description of the signals is given in Section 7 Receive Data Path
Operation.
Receive Data Bus (RPATH7–RPATH0)
This 8-bit, CMOS-level, unidirectional data bus is used for byte transfers from the MAC
to the FSI. These lines are used at different times to carry either a pair of data symbols
belonging to a received frame, status information describing the frame and why it
ended, or frame status indicators.
Receive Parity (RPRITY)
This output signal indicates the parity of the RPATHx bus; the RCCTLx not affected.
The MAC always generates odd or even parity according to the RX_PARITY bit value in
control register A. There is no way to disable parity generation for this signal.
Receive Abort (RABORT)
This TTL-level input signal indicates that the FSI cannot accept any more data from the
MAC (e.g., due to buffer overflow). RABORT must be asserted during a DATA transfer
cycle; RABORT is ignored during FILLER, START_DATA, END_DATA, and
FRAME_STATUS transfers. RABORT must be negated immediately upon detection of
an END_DATA transfer.
4.5 TRANSMIT SYSTEM INTERFACE
The transmit system interface provides the data path from the FSI. to the MAC.
Transmit Control Signals (TXCTL1–TXCTL0)
These TTL-level input signals are used to indicate to the MAC the type of data
presented on the TPATHx bus. These signals are synchronous to BYTCLK and
TPATHx. A detailed description of these signals is given in Section 8 Transmit Data
Path Operation.
Transmit Data Bus (TPATH7–TPATH0)
This 8-bit, TTL-level, unidirectional data bus is used for byte transfers from the FSI to
the MAC. These lines are used at different times to carry either packet data (either data
to be sent or part of the packet request header) or extra control information. These
signals must be synchronous to BYTCLK.
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