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參數(shù)資料
| 型號(hào)： | GS1582-IBE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX |
| 中文描述： | 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行 |
| 文件頁數(shù)： | 99/114頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | GS1582-IBE3 |
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GS1582 Data Sheet
40117 - 1 November 2007
99 of 114
802h
Reserved
15
Reserved
R
0
AES_ERRD
14
Stereo Pair D audio input parity error when using AES
format. Automatically cleared when read.
Reference:
Section 4.7.17.1 on page 53
.
R
0
AES_ERRC
13
Stereo Pair C audio input parity error when using AES
format. Automatically cleared when read.
Reference:
Section 4.7.17.1 on page 53
.
R
0
AES_ERRB
12
Stereo Pair B audio input parity error when using AES
format. Automatically cleared when read.
Reference:
Section 4.7.17.1 on page 53
.
R
0
AES_ERRA
11
Stereo Pair A audio input parity error when using AES
format. Automatically cleared when read.
Reference:
Section 4.7.17.1 on page 53
.
R
0
ACPG4_DET
10
Set while Group 4 audio control packets are detected.
Reference:
Section 4.7.2 on page 37
.
R
0
ACPG3_DET
9
Set while Group 3 audio control packets are detected.
Reference:
Section 4.7.2 on page 37
.
R
0
ACPG2_DET
8
Set while Group 2 audio control packets are detected.
Reference:
Section 4.7.2 on page 37
.
R
0
ACPG1_DET
7
Set while Group 1 audio control packets are detected.
Reference:
Section 4.7.2 on page 37
.
R
0
ADPG4_DET
6
Set while Group 4 audio data packets are detected.
Reference:
Section 4.7.2 on page 37
.
R
0
ADPG3_DET
5
Set while Group 3 audio data packets are detected.
Reference:
Section 4.7.2 on page 37
.
R
0
ADPG2_DET
4
Set while Group 2 audio data packets are detected.
Reference:
Section 4.7.2 on page 37
.
R
0
ADPG1_DET
3
Set while Group 1 audio data packets are detected.
Reference:
Section 4.7.2 on page 37
.
R
0
ACS_APPLY_WAITB
2
Set while the GS1582 is waiting for a status boundary in
the Group B group before applying the ACSR[183:0]
data to that group.
Reference:
Section 4.7.18 on page 55
.
R
0
ACS_APPLY /
ACS_APPLY_WAITA
1
Set while the GS1582 is waiting for a status boundary in
Group A before applying the ACSR[183:0] data.
Reference:
Section 4.7.18 on page 55
.
R/W
0
ACS_REGEN
0
Specifies that Audio Channel Status of all channels
should be replaced with ACSR[183:0] field.
0: Do not replace Channel Status
1: Replace Channel Status of all channels
Reference:
Section 4.7.18 on page 55
.
R/W
0
Table 4-45: HD Audio Configuration and Status Registers
Address
Register Name
Bit
Description
R/W
Default
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4900B | SD Clock and Timing Generator with GENLOCK |
| GS4900BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4901B | SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4910B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS-158N | 制造商:Taiyo Electric Ind. 功能描述: |
| GS15A | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop |
| GS15A/B | 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS15A/B-2P1J | 制造商:Mean Well 功能描述: |
| GS15A/B-6P1J | 制造商:Mean Well 功能描述: |
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