參數(shù)資料
型號(hào): GS1582-IBE3
廠商: Gennum Corporation
英文描述: IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX
中文描述: 多速率的電纜驅(qū)動(dòng)器,音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁(yè)數(shù): 55/114頁(yè)
文件大?。?/td> 1224K
代理商: GS1582-IBE3
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GS1582 Data Sheet
40117 - 1 November 2007
55 of 114
Figure 4-22: Serial Audio Input: Left Justified; LSB First
Figure 4-23: Serial Audio Input: Right Justified; MSB First
Figure 4-24: Serial Audio Input: Right Justified; LSB First
Figure 4-25: I
2
S Audio Input
4.7.18 Audio Channel Status Input
The Audio Channel Status block information can be programmed via the host
interface using the ACSR[183:0] register (see
Table 4-17: Audio Channel Status
Information Register Settings
). The Audio Channel Status input consists of 24
bytes transmitted 1 bit per audio sample over a 192-frame sequence. The same
audio channel status information is embedded for each sample in an audio frame,
over all 8 input channels. The GS1582 generates the Z bit to denote the start of the
Audio Channel Status block.
When the ACS_REGEN bit in the host interface is set HIGH, the GS1582 will use
the Audio Channel Status information programmed in the ACSR[183:0] register to
replace the Audio Channel Status block in all eight channels. The CRC for the
Audio Channel Status block will be calculated automatically. The GS1582 will use
this new Audio Channel Status information only when ACS_APPLY is HIGH and a
new status boundary at this point. When the ACS_APPLY is set, the
APPLY_WAITA host interface bit will be asserted until a status boundary for audio
WCLK
ACLK
AIN
0
LSB
1
23
22
21
20
19
18
17
2
MSB
LSB
MSB
Channel A (Left)
Channel B (Right)
0
1
23
22
21
20
19
18
17
2
WCLK
ACLK
AIN
23
MSB
22
0
1
2
20
17
1
8
19
21
LSB
MSB
LSB
Channel A (Left)
Channel B (Right)
23
22
0
1
2
20
17
1
8
19
21
WCLK
ACLK
AIN
0
LSB
1
23
22
21
3
6
5
4
2
MSB
0
LSB
1
23
22
21
3
6
5
4
2
MSB
Channel A (Left)
Channel B (Right)
WCLK
ACLK
AIN
23
MSB
22
0
1
2
3
4
5
6
7
LSB
23
MSB
22
0
1
2
3
4
5
6
7
LSB
Channel A (Left)
Channel B (Right)
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