參數(shù)資料
型號: GS1582-IBE3
廠商: Gennum Corporation
英文描述: IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX
中文描述: 多速率的電纜驅(qū)動器,音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁數(shù): 36/114頁
文件大?。?/td> 1224K
代理商: GS1582-IBE3
GS1582 Data Sheet
40117 - 1 November 2007
36 of 114
In order to return to normal operation from standby mode, the STANDBY pin must
be set to LOW. Once normal operation is resumed, the GS1582 will re-lock to the
reference PCLK. The recovery time from standby mode is the same as initial
power-up but no reset is required. Once the GS1582 re-locks to the reference
PCLK, operation is resumed according to the configuration held before entering
standby mode.
4.7 Audio Multiplexer
Up to eight channels of audio may be embedded into the GS1582 video data
stream in accordance with SMPTE 299M and SMPTE 272M. The audio data is
input in two groups of four channels, with corresponding clock signals.
The audio input signal formats supported include AES/EBU and three other
industry standard serial digital formats. 16, 20 and 24-bit audio sample sizes are
supported at 48kHz synchronous for SD formats and 48kHz synchronous or
asynchronous for HD formats.
Additional audio processing features include audio mute, individual channel
enable, channel re-mapping, audio group replacement, cascade, group selection,
and audio channel status insertion.
The audio system clock can be provided by Gennum’s GEN-Clocks
TM
series of
clock generation IC’s. In serial formats, the audio clocks required by the core are
two word clocks and two signals that are a multiple of 64fs.
The SD audio multiplexer core is compliant with SMPTE 272M A and C. The HD
audio multiplexer core is fully compliant with SMTPE 299M.
4.7.1 Audio Core Configurations
Figure 4-10
shows the top level block diagrams of both the SD and HD multiplexer
cores.
Each group of audio has one word clock signal and one audio clock signal. Data
present at Ain_1/2 and Ain_3/4 share clocks present at WCLK1 and ACLK1, while
data present at Ain_5/6 and Ain_7/8 share clocks present at WCLK2 and ACLK2.
Table 4-2: Standby Power Consumption
Standby Condition
Typical Power Consumption (mW)
STANDBY asserted
125
STANDBY asserted
Parallel data and clock inactive
100
STANDBY asserted
3.3V supply removed from CD_VDD
35
STANDBY asserted
Parallel data and clock inactive
3.3V supply removed from CD_VDD
<10
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