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| 型號(hào)： | GS1582-IBE3 |
| 廠(chǎng)商： | Gennum Corporation |
| 英文描述： | IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX |
| 中文描述： | 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行 |
| 文件頁(yè)數(shù)： | 9/114頁(yè) |
| 文件大?。?/td> | 1224K |
| 代理商： | GS1582-IBE3 |
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GS1582 Data Sheet
40117 - 1 November 2007
9 of 114
A3
F/DE
Synchronous
with PCLK
Input
PARALLEL DATA TIMING
Signal levels are LVCMOS/LVTTL compatible.
TIM_861 = LOW:
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing
TRS signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2 and
should be set LOW for all lines in field 1 and for all lines in progressive
scan systems.
The F signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The DE signal is used to indicate the active video period. DE is HIGH for
active data and LOW for blanking. See
Section 4.3.1
and
Section 4.3.2
for timing details.
The DE signal is ignored when DETECT_TRS = HIGH.
A4
H/HSYNC
Synchronous
with PCLK
Input
PARALLEL DATA TIMING
Signal levels are LVCMOS/LVTTL compatible.
TIM_861 = LOW:
The H signal is used to indicate the portion of the video line containing
active video data, when DETECT_TRS is set low.
Active Line Blanking
The H signal should be set HIGH for the entire horizontal blanking
period, including the EAV and SAV TRS words, and LOW otherwise.
This is the default setting.
TRS Based Blanking (H_CONFIG = 1
h
)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and LOW
otherwise.
The H signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The HSYNC signal indicates horizontal timing. See
Section 4.3.1
for
timing details.
The HSYNC signal is ignored when DETECT_TRS = HIGH.
A5, E1, G10,
K8
CORE_VDD
Non
Synchronous
Input
Power
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
A6, B6
PD_VDD
Analog
Input
Power
Power supply connection for the phase detector. Connect to +1.8V DC
analog.
A7
LF
Analog
Input
PLL loop filter connection.
A8
VCO_VCC
Analog
Output
Power
Power supply for the external voltage controlled oscillator.
2.5V DC supplied by the device to the external VCO.
A9
VCO
Analog
Input
Input from external VCO.
A10
CP_VDD
Analog
Input
Power
Power supply connection for the charge pump and on chip VCO
regulator. Connect to +3.3V DC analog.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4900B | SD Clock and Timing Generator with GENLOCK |
| GS4900BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4901B | SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4910B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS-158N | 制造商:Taiyo Electric Ind. 功能描述: |
| GS15A | 制造商:MEANWELL 制造商全稱(chēng):Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop |
| GS15A/B | 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS15A/B-2P1J | 制造商:Mean Well 功能描述: |
| GS15A/B-6P1J | 制造商:Mean Well 功能描述: |
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