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參數(shù)資料
| 型號(hào)： | GS1582-IBE3 |
| 廠(chǎng)商： | Gennum Corporation |
| 英文描述： | IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX |
| 中文描述： | 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行 |
| 文件頁(yè)數(shù)： | 74/114頁(yè) |
| 文件大?。?/td> | 1224K |
| 代理商： | GS1582-IBE3 |
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GS1582 Data Sheet
40117 - 1 November 2007
74 of 114
4.11 Internal ClockCleaner
TM
PLL
To obtain a clean clock signal for serialization and transmission, an external VCO
signal is locked to the input PCLK via the GS1582's integrated phase-locked loop.
This high quality analog PLL has a bang-bang implementation, which automatically
narrows the loop bandwidth in the presence of jitter, allowing the GS1582 to
significantly attenuate jitter on the incoming PCLK.
4.11.1 External VCO
The GS1582 requires the GO1555 external voltage controlled oscillator as part of
its internal PLL.
Power for the external VCO is generated by the GS1582 from an integrated voltage
regulator. The internal regulator uses +3.3V supplied on the CP_VDD / CP_GND
pins to provide +2.5V on the VCO_VCC / VCO_GND pins.
The external VCO produces a 1.485GHz signal for the PLL, input on the VCO pin
of the device. See
Typical Application Circuit (Part A) on page 108
.
NOTE: The VCO_VCC output voltage is guaranteed to be 2.5V only when
supplying power to the GO1555. The VCO_VCC pin should not be shorted to GND
under any circumstances.
4.11.2 Loop Filter
The GS1582 PLL loop filter is an external first order filter formed by a series RC
connection as shown in the
Typical Application Circuit (Part A) on page 108
. The
loop filter resistor value sets the bandwidth of the PLL and the capacitor value
controls its stability and lock time. A loop filter resistor value between 1
Ω
to 20
Ω
and a loop filter capacitor value between 1μF to 33μF are recommended.
The GS1582 uses a non-linear, bang-bang, PLL, therefore its bandwidth scales
with the input jitter amplitude - greater input jitter results in a smaller loop bandwidth
causing more of the input jitter to be rejected. For a given input jitter amplitude, a
smaller loop filter resistor produces a narrower loop bandwidth. With an input jitter
amplitude of 300ps, for example, the PLL bandwidth can be adjusted from 2KHz to
Table 4-39: Serial Digital Output Rates
Supplied PCLK Rate
Serial Digital
Output Rate
Pin Settings
SD/HD
20bit/10bit
74.25 or
74.25/1.001 MHz
1.485 or
1.485/1.001Gb/s
LOW
HIGH
148.5 or
148.5/1.001MHz
1.485 or
1.485/1.001Gb/s
LOW
LOW
13.5MHz
270Mb/s
HIGH
HIGH
27MHz
270Mb/s
HIGH
LOW
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS-158N | 制造商:Taiyo Electric Ind. 功能描述: |
| GS15A | 制造商:MEANWELL 制造商全稱(chēng):Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop |
| GS15A/B | 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS15A/B-2P1J | 制造商:Mean Well 功能描述: |
| GS15A/B-6P1J | 制造商:Mean Well 功能描述: |
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