參數(shù)資料
型號(hào): GS1582-IBE3
廠商: Gennum Corporation
英文描述: IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX
中文描述: 多速率的電纜驅(qū)動(dòng)器,音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁(yè)數(shù): 20/114頁(yè)
文件大?。?/td> 1224K
代理商: GS1582-IBE3
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GS1582 Data Sheet
40117 - 1 November 2007
20 of 114
Mismatch in rise/fall time
Δ
t
r
,
Δ
t
f
35
ps
Duty Cycle Distortion
1
5
%
5
Overshoot
SD/HD=0
5
10
%
5
SD/HD=1
3
8
%
5
Output Return Loss
ORL
5 MHz - 1.485 GHz
18
dB
6
Serial Output Intrinsic Jitter
t
OJ
Pseudorandom and
SMPTE Colour Bars
HD signal
35
80
ps
2
t
OJ
Pseudorandom and
SMPTE Colour Bars
SD signal
100
200
ps
3
GSPI
GSPI Input Clock Frequency
f
SCLK
50% levels
3.3V or 1.8V operation
10
MHz
GSPI Input Clock Duty Cycle
DC
SCLK
40
50
60
%
GSPI Input Data Setup Time
1.5
ns
GSPI Input Data Hold Time
1.5
ns
GSPI Output Data Hold Time
15pF load
1.5
ns
CS low before SCLK rising
edge
50% levels
3.3V or 1.8V operation
1.5
ns
Time between end of
command word (or data in
Auto-Increment mode) and
the first SCLK of the following
data word - write cycle
50% levels
3.3V or 1.8V operation
37.1
ns
Time between end of
command word (or data in
Auto-Increment mode) and
the first SCLK of the following
data word - read cycle
50% levels
3.3V or 1.8V operation
148.4
ns
CS high after SCLK rising
edge
50% levels
3.3V or 1.8V operation
37.1
ns
NOTES:
1. See
’Device Reset’ on page 107, Figure 4-33
.
2. Alignment Jitter = measured from 100kHz to 148.5MHz
3. Alignment Jitter = measured from 1kHz to 27MHz
4. Input setup and hold time is dependent on the rise and fall time on the parallel input. Parallel clock and data with rise time or fall time
greater than 500ps require larger setup and hold times.
5. Single Ended into 75
Ω
external load.
6. ORL depends on board design. The GS1582 achieves this specification on Gennum’s evaluation boards.
Table 2-3: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
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