參數(shù)資料
型號(hào)： GS1582-IBE3
廠商： Gennum Corporation
英文描述： IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX
中文描述： 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁數(shù)： 71/114頁
文件大小： 1224K
代理商： GS1582-IBE3
GS1582 Data Sheet
40117 - 1 November 2007
71 of 114
4.9.4.2 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the
GS1582 will remap all codes within the active picture between the values of 3FCh
and 3FFh to 3FBh. All codes within the active picture area between the values of
000h and 003h will be remapped to 004h.
In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit
values.
4.9.4.3 EDH Generation and Insertion
When operating in SD mode, (SD/HD = HIGH), the GS1582 will generate and
insert complete EDH packets. Packet generation and insertion will only take place
if the EDH_CRC_INS bit of the IOPROC_DISABLE register is set LOW.
The GS1582 will generate all of the required EDH packet data including all ancillary
data preambles DID, DBN, DC, reserved code words, and the checksum.
Calculation of both full field (FF) and active picture (AP) CRC's will be carried out
by the device.
SMPTE RP165 specifies the calculation ranges and scope of EDH data for
standard 525 and 625 component digital interfaces. The GS1582 uses these
standard ranges by default.
If the received video format does not correspond to 525 or 625 digital component
video standards, then the ranges will be determined from the received TRS ID
words or supplied H_Blanking, V_Blanking, and F_Digital timing signals; or
HSYNC, VSYNC and DE CEA 861 timing signals. See
HVF Timing on page 28
,
and
CEA 861 Timing on page 29
.
The first active and full field pixel will always be the first pixel after the SAV TRS
code word. The last active and full field pixel will always be the last pixel before the
start of the EAV TRS code words.
EDH error flags (EDH, EDA, IDH, IDA and UES) for ancillary data, full field and
active picture will also be inserted when the corresponding bit of the EDH_FLAG
register is set HIGH. (
Table 4-38
).
NOTE 1: The EDH flag registers must be updated once per field. The prepared
EDH packet will be inserted at the appropriate line according to SMPTE RP165.
The start pixel position of the inserted packet will be based on the SAV position of
that line such that the last byte of the EDH packet (the checksum) will be placed in
the sample immediately preceding the start of the SAV TRS word.
NOTE 2: EDH packets will not be inserted if there is insufficient room in the HANC
space.
相關(guān)PDF資料
PDF描述
GS4900B SD Clock and Timing Generator with GENLOCK
GS4900BCNE3 SD Clock and Timing Generator with GENLOCK
GS4901B SD Clock and Timing Generator with GENLOCK
GS4901BCNE3 SD Clock and Timing Generator with GENLOCK
GS4910B HD/SD/Graphics Clock and Timing Generator with GENLOCK
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS-158N 制造商:Taiyo Electric Ind. 功能描述:
GS15A 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop
GS15A/B 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V
GS15A/B-2P1J 制造商:Mean Well 功能描述:
GS15A/B-6P1J 制造商:Mean Well 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*