參數(shù)資料
型號： GS1582-IBE3
廠商： Gennum Corporation
英文描述： IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX
中文描述： 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁數(shù)： 73/114頁
文件大?。?/td> 1224K
代理商： GS1582-IBE3
GS1582 Data Sheet
40117 - 1 November 2007
73 of 114
4.9.4.4 Ancillary Data Checksum Generation and Insertion
The GS1582 will calculate checksums for all detected ancillary data packets
presented to the device. These calculated checksum values are inserted into the
data stream prior to serialization.
Ancillary data checksum generation and insertion will only take place if the
ANC_CSUM_INS bit of the IOPROC_DISABLE register is set LOW.
NOTE: The GS1582 will recalculate the checksum and, if incorrect, will re-insert
the correct value. However, the GS1582 does not check the correctness of the
parity bit. That is, if all the bits from 0 to 8 in the checksum word are correct and
only bit 9 (the parity bit, which is the inverse of bit 8) is incorrect, then the checksum
word is not re-calculated. If even one of bit 0 to bit 8 has an incorrect value, then
the checksum word is re-calculated and re-inserted.
4.9.4.5 Line Based CRC Generation and Insertion
The GS1582 will generate and insert line based CRC words into both the luma and
chroma channels of the data stream. This feature is only available in HD mode and
is enabled by setting the CRC_INS bit of the IOPROC_DISABLE register LOW.
4.9.4.6 HD Line Number Generation and Insertion
In HD mode, the GS1582 will calculate and insert line numbers into the luma and
chroma channels of the output data stream.
Line number generation is in accordance with the relevant HD video standard as
determined by the device, see
Automatic Video Standard Detection on page 65
.
This feature is enabled when SD/HD = LOW, and the LNUM_INS bit of the
IOPROC_DISABLE register is set LOW.
4.9.4.7 TRS Generation and Insertion
The GS1582 can generate and insert 10-bit TRS code words into the data stream
as required. This feature is enabled by setting the TRS_INS bit of the
IOPROC_DISABLE register LOW.
TRS word generation will be performed in accordance with the timing parameters
generated by the device which will be locked either to the received TRS ID words,
the supplied H_Blanking, V_Blanking, and F_Digital timing signals, or the CEA 861
timing signals, see
HVF Timing on page 28
and
CEA 861 Timing on page 29
.
4.10 Parallel to Serial Conversion
The GS1582 can accept either 10-bit or 20-bit parallel data in both SD and HD
modes. The supplied PCLK rate must correspond to the settings of the SD/HD and
20bit/10bit pins as shown in
Table 4-39
.
相關(guān)PDF資料
PDF描述
GS4900B SD Clock and Timing Generator with GENLOCK
GS4900BCNE3 SD Clock and Timing Generator with GENLOCK
GS4901B SD Clock and Timing Generator with GENLOCK
GS4901BCNE3 SD Clock and Timing Generator with GENLOCK
GS4910B HD/SD/Graphics Clock and Timing Generator with GENLOCK
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS-158N 制造商:Taiyo Electric Ind. 功能描述:
GS15A 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop
GS15A/B 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V
GS15A/B-2P1J 制造商:Mean Well 功能描述:
GS15A/B-6P1J 制造商:Mean Well 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*