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參數(shù)資料
| 型號： | GS1582-IBE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX |
| 中文描述： | 多速率的電纜驅(qū)動器，音頻多路復用器和ClockCleaner⑩串行 |
| 文件頁數(shù)： | 75/114頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | GS1582-IBE3 |
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GS1582 Data Sheet
40117 - 1 November 2007
75 of 114
40KHz by varying the loop filter resistor, as shown in
Table 4-40: Loop Filter
Component Values
. For use with the GEN-Clocks
TM
timing generators, a narrow
loop bandwidth is recommended.
Increasing the loop filter capacitor value increases the stability of the PLL, but
results in a longer lock time. For loop filter resistors smaller than 7
Ω
, a capacitor
value of 33μF is recommended, while larger resistor values can accommodate
smaller capacitors. Sample combinations of the loop filter resistor and capacitor
values are shown in
Table 4-40: Loop Filter Component Values
, along with the
resulting loop bandwidth. Additional loop bandwidths can be achieved by using
different loop filter resistor values.
4.11.3 Lock Detect Output
The LOCKED output will be asserted HIGH when the internal PLL has locked to
the input PCLK signal. In the absence of the PCLK, when frequency lock has not
been achieved, and during device reset, the LOCKED output will be LOW.
Lock time, the time it takes for the internal PLL to frequency-lock to the reference
PCLK following power-up or standby, is determined by the loop filter capacitor
value chosen. A 1
μ
F loop filter capacitor, for example, will result in lock times of
less than 500
μ
s. A 33
μ
F loop filter capacitor, on the other hand, will result in a lock
time of greater than 5s.
NOTE 1: When the PLL is in the process of locking to the reference PCLK, the
LOCKED pin may generate LOW and HIGH pulses. The durations of these pulses
are dependent on the loop filter capacitor value, but do not exceed 30ms. Once the
PLL has achieved frequency lock, the LOCKED pin will remain HIGH and not
change state.
NOTE 2: When the GS1582 is placed in standby mode, the value of LOCKED is
maintained although the PLL does lose lock to the reference PCLK. When
STANDBY is released, the PLL will re-lock. During this time, if the LOCKED pin
was previously HIGH, it will de-assert approximately 6
μ
s later, and re-assert once
the PLL has re-locked to the input PCLK.
Table 4-40: Loop Filter Component Values
Loop Filter
Resistor
Value
Typical Loop
Bandwidth*
Recommended
Loop Filter
Capacitor
Value
Comments
1
Ω
2kHz
33
μ
F
Narrow bandwidth - provides
maximum jitter reduction. Long
lock-time.
7
Ω
8kHz
10
μ
F
20
Ω
40kHz
1
μ
F
Wide bandwidth. Fast lock-time.
* Measured with 300ps pk-pk input jitter on PCLK
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