參數(shù)資料
型號: GS1582-IBE3
廠商: Gennum Corporation
英文描述: IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX
中文描述: 多速率的電纜驅(qū)動器,音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁數(shù): 76/114頁
文件大?。?/td> 1224K
代理商: GS1582-IBE3
GS1582 Data Sheet
40117 - 1 November 2007
76 of 114
4.12 Serial Digital Output
The GS1582 includes a SMPTE compliant current mode differential serial digital
cable driver with automatic slew rate control. The serial output has improved eye
quality, exceptional ORL performance, and reduced duty cycle distortion.
The cable driver uses a separate +3.3V DC power supply provided via the
CD_VDD and CD_GND pins.
To enable the output, SDO_EN/DIS must be set HIGH. Setting the SDO_EN/DIS
signal LOW will set the SDO and SDO output pins to high impedance, resulting in
reduced device power consumption.
4.12.1 Output Swing
Nominally, the voltage swing of the serial digital output is 800mVp-p single-ended
into a 75
Ω
load. This is set externally by connecting the RSET pin to CD_VDD
through 750
Ω
±1% resistor
.
4.13 GSPI Host Interface
The GS1582 host interface, also called the Gennum Serial Peripheral Interface
(GSPI), provides access to configuration/status registers for the video processing
and SD and HD audio processing functions of the chip.
By default, the device will be “l(fā)ive at power up” with all major functional blocks
active in the defined default operating conditions described below.
Dedicated configuration pins are provided for basic configuration of the device.
The host interface is provided to allow optional configuration of some of the more
advanced functions and operating modes of the device.
To simplify host interface access to the configuration and status registers, a single
contiguous register map is provided for the video and audio functions.
Registers are grouped by like function and wherever possible functional
configuration will not be spread across multiple registers.
The GSPI is comprised of a serial data input signal (SDIN), serial data output signal
(SDOUT), an active low chip select (CS), and a burst clock (SCLK). The burst clock
must have a duty cycle between 40% and 60% while active.
Because these pins are shared with the JTAG interface port, an additional control
signal pin JTAG/HOST is provided. When JTAG/HOST is LOW, the GSPI interface
is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS are inputs to the device.
The SDOUT loops the SDIN back out when GSPI is in write mode, or when CS is
HIGH, allowing multiple devices to be connected in series. During reset, SDOUT is
held in high-impedance mode. The interface is illustrated in the
Figure 4-26
.
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