參數(shù)資料
型號(hào)： GS1582-IBE3
廠商： Gennum Corporation
英文描述： IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX
中文描述： 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁數(shù)： 54/114頁
文件大小： 1224K
代理商： GS1582-IBE3
GS1582 Data Sheet
40117 - 1 November 2007
54 of 114
Figure 4-19: AES/EBU Sub-frame Formatting
The audio clock to data timing and input format is shown in
Figure 4-20
.
Figure 4-20: AES/EBU Audio Input Format
NOTE: Due to the bi-phase mark encoding used in AES/EBU mode, for each logic
1 bit period, there will be an additional transition. In
Figure 4-20
, this additional
transition is not shown.
In the event of a parity error in Stereo Pair A in AES/EBU mode, the GS1582 will
set the AES_ERRA bit in the host interface. The same is true of AES_ERRB for
Stereo Pair B, AES_ERRC for Stereo Pair C, and AES_ERRD for Stereo Pair D.
NOTE: In order to read back the parity error bits of register 1, register 2 must be
read first to trigger an update of these bits. The parity error bits will be cleared when
read from register 1.
4.7.17.2 Serial Audio Input Mode
In serial audio input modes, the GS1582 clocks the audio data input on the rising
edge of the ACLK_1/2 input clock at 64fs (3.072MHz), as shown in
Figure 4-21
,
Figure 4-24
and
Figure 4-25
below.
Figure 4-21: Serial Audio Input: Left Justified; MSB First
24 -bit
Sync
Preamble
24-bit Audio Sample Word
V U C P
0
3
4
27 2
8
29 30 31
Channel Status Bit
Validity Bit
User Data Bit
Parity Bit
20-bit
Sync
Preamble
20-bit Audio Sample Word
V U C P
0
3
4
27 2
8
29 30 31
LSB
MSB
LSB
MSB
7
8
Aux
Data
16-bit
Sync
Preamble
16-bit Audio Sample Word
V U C P
0
3
4
27 2
8
29 30 31
LSB
MSB
7
8
Aux
Data
11 12
Set To
Zero
AIN
MSB
2
8
27
8
7
2
1
0
LSB
3
4
5
6
29
30
31
V
U
C
P
AUX
Preamble
MSB
2
8
27
8
7
2
1
LSB
3
4
5
6
29
30
31
V
U
C
P
AUX
Preamble
0
WCLK
ACLK
AIN
23
MSB
22
0
1
2
3
4
5
6
21
LSB
23
MSB
22
0
1
2
3
4
5
6
21
LSB
Channel A (Left)
Channel B (Right)
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