參數(shù)資料
型號(hào)： GS1582-IBE3
廠商： Gennum Corporation
英文描述： IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX
中文描述： 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁數(shù)： 108/114頁
文件大?。?/td> 1224K
代理商： GS1582-IBE3
GS1582 Data Sheet
40117 - 1 November 2007
108 of 114
5. Application Reference Design
5.1 Typical Application Circuit (Part A)
AUDIO INTERRUPT
STANDBY
TIMING_SELECT
AUDIO CHANNELS 7 & 8
AUDIO CHANNELS 5 & 6
JTAG/HOST
PCLK INPUT (from GS4911B)
LOCKED
GND_A
BNC
CONTROL SIGNALS
GND_A
BNC
BLANK
PRIMARY GROUP AUDIO CLOCK
PRIMARY AUDIO GROUP ENABLE
IOPROC_EN/DIS
20bit/10bit
FVH INPUT[2:0] (from GS4911B)
SDO_EN/DIS
AUDIO CHANNELS 1 & 2
AUDIO SIGNALS
AUDIO CHANNELS 3 & 4
SECONDARY GROUP WORD CLOCK
AIN7_8
A_INT
EN_GRP1
WCLK_2
ACLK_1
EN_GRP2
AIN3_4
AIN1_2
AIN5_6
ACLK_2
WCLK_1
PRIMARY GROUP WORD CLOCK
DVB_ASI
STANDBY
RESETn
SDO_EN/DISn
BLANKn
JTAG/HOSTn
SMPTE_BYPASSn
DETECT_TRS
20bit/10bitn
IOPROC_EN/DISn
TIMING_SEL
DETECT_TRS
+3.3V_CD
SD/HD
SD/HDn
DVB-ASI
10n
+3.3V
1u
+1.8V_A
0R
1u
0R
10n
10n
+1.8V
DATA_IN14
10n
GSPI[3:0]
10KR
GND_A
DATA_IN15
A_INT
75R
5n6
75R
5n6
SDIN
SDOUT
SCLK
4u7
4u7
+3.3V
22k
R and L form the Output Return
Loss compensation Network.
SUBJECT TO CHANGE
H/HSYNC_GS4911B
DATA_IN16
EN_GRP1
ACLK_1
WCLK_1
AIN1_2
AIN3_4
75R
10n
75R
DATA_IN17
IO_VDD
+1.8V
PCLK_1582
1
2
1u
1
2
1u
10n
10n
0R
SMPTE_BYPASS
+3.3V
0R
DATA_IN18
NP
NP
DATA_IN19
RESETn
SMPTE_BYPASSn
10n
VCO_VCC
C*
EN_GRP2
ACLK_2
WCLK_2
AIN5_6
AIN7_8
SDO_EN/DISn
DETECT_TRS
DVB_ASI
JTAG/HOSTn
ANC_BLANKn
IOPROC_EN/DISn
20bit/10bitn
STANDBY
TIMING_SEL
SD/HDn
VCO_GND
3R3
DATA_IN0
R*
DATA_IN1
SECONDARY AUDIO GROUP ENABLE
VCO_GND
DATA_IN2
DATA_IN3
CSn
RESET
CP_RES
LF
B7
A7
VCO_VCC
VCO_GND
A8
B9
VCO_GND
B8
C
E
VCO
A9
TIM_861
G3
PCLK
B4
I
G
DIN18
DIN17
DIN16
DIN15
A2
A1
B2
B1
DIN19
B3
C
A
C
B
C
K
GRP1_EN/DIS
ACLK_1
AIN_1/2
AIN_3/4
H6
K7
J7
J6
K6
DETECT_TRS
STANDBY
F3
D3
C
E
C
G
P
A
P
B
C
D
DIN14
DIN13
C2
C1
C
C
C
B
NC
NC
NC
NC
D6
D7
D8
E4
DVB_ASI
JTAG/HOST
G5
H8
LOCKED
H4
GRP2_EN/DIS
ACLK_2
WCLK_2
AIN_5/6
AIN_7/8
H5
K5
J5
J4
K4
DIN12
DIN11
C3
D1
NC
E8
F4
NC
F8
SD/HD
E3
C
E
C
E
I
H
DIN10
DIN9
D2
F1
C
J
C
G
20BIT/10BIT
SDO_EN/DIS
G4
D4
C
F
C
A
I
G
DIN8
F2
H1
C
F
C
F
C
E
IOPROC_EN/DIS
G7
SMPTE_BYPASS
G6
RESET
G8
BLANK
H3
DIN6
DIN5
H2
J1
C
D
C
E
AUDIO_INT
H7
CS_TMS
SCLK_TCK
SDIN_TDI
K9
J10
K10
SDOUT_TDO
J9
H/HSYNC
A4
DIN4
DIN3
J2
K1
C
F
P
C
P
C
P
C
V/VSYNC
C4
I
H
DIN2
DIN1
K2
J3
RSET
F10
C
E
SDO
SDO
C10
D10
C
C
F/DE
A3
DIN0
K3
GS1582
PLACE AS CLOSE AS
POSSIBLE TO THE PINS
OF THE GS1582.
CONNECT DIRECTLY
TO PINS OF GS1582.
DATA_IN4
ANALOG POWER FILTERING
GND_A
DATA_IN5
+1.8V_A
GND_A
DATA_IN6
PARALLEL DATA INPUT[19:0]
DATA_IN7
GND_A
+3.3V_CD
GND_A
DATA_IN8
GND_A
DATA_IN9
DATA_IN10
VCO_GND
VCO_GND
VCO_GND
DATA_IN11
VCO_GND
VCO_GND
VCO_VCC
VCO_GND
2.5V INTERNAL ISOLATED POWER
VCTR
5
G
4
G
8
GND
2
VCC
7
O/P
1
NC
3
GND
6
GO1555
10n
1
2
33uF
+3.3V_CD
750R +/- 1%
DATA_IN13
V/VSYNC_GS4911B
F/DE_GS4911B
+3.3V_CD
1u
SECONDARY GROUP AUDIO CLOCK
1u
0R
10n
(ACLK and WCLK may be supplied by
GS4911B audio clock outputs.)
*R & C:
Refer to Section 4.11.2 for
Loop Filter Component Values.
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