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參數(shù)資料
| 型號(hào)： | GS1582-IBE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX |
| 中文描述： | 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行 |
| 文件頁數(shù)： | 50/114頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | GS1582-IBE3 |
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GS1582 Data Sheet
40117 - 1 November 2007
50 of 114
4.7.12 Channel and Group Activation
Multiplexing of individual audio channels is enabled by setting the ACTn bits in host
interface register 0Ch. When set HIGH, the corresponding audio channel is
multiplexed into the video data stream. Channels designated as not active (ACTn
set LOW) will be embedded with null samples (all bits set to zero). When all ACTn
bits are set LOW, no audio data packets will be multiplexed.
When ACT[1-4] are set LOW, the audio group set in IDA[1:0] will not be
multiplexed. Similarly, when ACT[5-8] are set LOW, the audio group set in IDB[1:0]
will not be multiplexed. This allows four channel, single group operation.
By default, all audio channels are enabled.
Refer to
Section 4.13.3
for HD and SD audio multiplexer status and configuration
registers.
4.7.13 ECC Error Detection & Correction (HD Mode Only)
The GS1582 will generate the error detection and correction fields in the audio data
packets.
All generated error detection and correction complies with SMPTE 299M.
4.7.14 Interrupt Control
The GS1582 can be programmed to assert the interrupt signal (AUDIO_INT, pin
H7) whenever an internal interrupt condition exists.
To enable a particular type of interrupt, the corresponding bit in the host interface
must be set. If the audio interrupt bit is un-masked, and the interrupt condition is
met, the the AUDIO_INT pin will go HIGH. For example, if the EN_ADPG_1 is
enabled, and the incoming video has embedded audio in group one, then the
AUDIO_INT pin will go HIGH.
Please refer to
Section 4.13.3
for HD and SD audio multiplexer status and
configuration registers for a complete listing of the audio interrupts.
4.7.15 Audio Clocks
The audio multiplexer has 4 clock inputs: ACLK_1, ACLK_2, WCLK_1 and
WCLK_2. For serial audio input modes ACLK_1/2
must be provided at 64fs, where
fs is the fundamental sampling frequency of 48kHz. An audio word clock at 48kHz
must also be supplied at the WCLK_1/2 inputs. For AES/EBU audio input mode,
the ACLK_1/2 and WLCK_1/2 inputs are not required. All required clocks will
automatically be derived from the AES/EBU preambles. ACLK_1/2 and WCLK_1/2
will be HIGH impedance in AES/EBU audio input mode.
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS-158N | 制造商:Taiyo Electric Ind. 功能描述: |
| GS15A | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop |
| GS15A/B | 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS15A/B-2P1J | 制造商:Mean Well 功能描述: |
| GS15A/B-6P1J | 制造商:Mean Well 功能描述: |
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