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參數(shù)資料
| 型號(hào)： | GS1582-IBE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX |
| 中文描述： | 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行 |
| 文件頁數(shù)： | 10/114頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | GS1582-IBE3 |
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GS1582 Data Sheet
40117 - 1 November 2007
10 of 114
B4
PCLK
–
Input
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode
PCLK = 74.25MHz or 74.25/1.001MHz
HD 10-bit mode
PCLK = 148.5MHz or 148.5/1.001MHz
SD 20-bit mode
PCLK = 13.5MHz
SD 10-bit mode
PCLK = 27MHz
B5, C5, D5,
E2, E5, E6,
E7, F5, F6,
F7, G9, J8
CORE_GND
Non
Synchronous
Input
Power
Ground connection for the digital core logic. Connect to digital GND.
C6, C7, C8
PD_GND
Analog
Input
Power
Ground connection for the phase detector. Connect to analog GND.
B7
CP_RES
–
Input
Charge pump current setting resistor.
B8, B9
VCO_GND
Analog
Output
Power
Ground pins for the VCO.
B10
CP_GND
Analog
Input
Power
Ground pin for the charge pump and PLL.
C4
V/VSYNC
Synchronous
with PCLK
Input
PARALLEL DATA TIMING
Signal levels are LVCMOS/LVTTL compatible.
TIM_861 = LOW:
The V signal is used to indicate the portion of the video field/frame that
is used for vertical blanking, when DETECT_TRS is set LOW.
The V signal should be set HIGH for the entire vertical blanking period
and should be set LOW for all lines outside of the vertical blanking
interval.
The V signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The VSYNC signal indicates vertical timing. See
Section 4.3.1
for timing
details.
The VSYNC signal is ignored when DETECT_TRS = HIGH.
C9, D9, E9,
F9
CD_GND
Analog
Input
Power
Ground connection for the serial digital cable driver. Connect to analog
GND.
C10, D10
SDO, SDO
Analog
Output
Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or
270Mb/s.
The slew rate of these outputs is automatically controlled to meet
SMPTE 292M and 259M requirements according to the setting of the
SD/HD pin.
Serial digital output signal from the internal cable driver.
NOTE: The SDO/SDO output signals will be set to high impedance
when RESET = LOW.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4900B | SD Clock and Timing Generator with GENLOCK |
| GS4900BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4901B | SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4910B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS-158N | 制造商:Taiyo Electric Ind. 功能描述: |
| GS15A | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop |
| GS15A/B | 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS15A/B-2P1J | 制造商:Mean Well 功能描述: |
| GS15A/B-6P1J | 制造商:Mean Well 功能描述: |
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