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參數(shù)資料
| 型號： | GS1582-IBE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX |
| 中文描述： | 多速率的電纜驅(qū)動器，音頻多路復(fù)用器和ClockCleaner⑩串行 |
| 文件頁數(shù)： | 58/114頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | GS1582-IBE3 |
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GS1582 Data Sheet
40117 - 1 November 2007
58 of 114
the GP1_WCLK_SRC[1:0] and GP2_WCLK_SRC[1:0] register.
Table 4-20: Audio
Clock Selection Host Interface Settings
shows the audio clock source for each
setting of the registers.
Each audio group consists of 4 channels, which share the same word clock.
Therefore, the audio data applied to each channel within the group must be the
same format and have identical word clock requirements.
NOTE: In AES mode, by default, word clock is extracted from channels 1/2 for
Audio group 1 and channels 5/6 for Audio group 2. If audio is applied only to 3/4 or
7/8 only, then no audio is embedded until the word clock source is changed from
channels 1/2 or 5/6, to channels 3/4 or 7/8.
4.7.21 GS1582 SD Audio FIFO Block
The GS1582 SD audio FIFO block contains the audio sample buffers. There is a
buffer per audio channel, which are 52 audio samples deep. At power up or reset,
the read pointer is held at the zero position until 26 samples have been written into
the FIFO. Once audio is being multiplexed, the offset between the audio sample
buffer read and write pointers is maintained at an average of 26 samples.
The position of the write pointer with respect to the read pointer is checked
constantly. If the write pointer is less than 6 samples ahead of the read pointer, a
sample is repeated from the read-side of the buffer. If the write pointer is less than
6 samples behind the read pointer, a sample is dropped. This scheme avoids buffer
underflow/overflow conditions.
The repeat or drop sample operation is performed up to a maximum of 28
consecutive times. After 28 repeat/drops, the GS1582 will mute (null audio packets
are embedded).
The audio buffer pointer offset can be reduced from 26 samples to 12 or 6 samples
using the OS_SEL[1:0] host interface register. The default setting is 26 samples
(see
Table 4-21
). When the OS_SEL[1:0] bits are set for 6-sample pointer offset,
no boundary checking is performed.
Table 4-20: Audio Clock Selection Host Interface Settings
GP_WCLK_SRC[1:0]
Word Clock Extraction
Source (AES Mode)
WCLK Source
(Serial Audio Mode)
00b
Channels 1/2
WCLK_1
01b
Channels 3/4
WCLK_1
10b
Channels 5/6
WCLK_2
11b
Channels 7/8
WCLK_2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS-158N | 制造商:Taiyo Electric Ind. 功能描述: |
| GS15A | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop |
| GS15A/B | 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS15A/B-2P1J | 制造商:Mean Well 功能描述: |
| GS15A/B-6P1J | 制造商:Mean Well 功能描述: |
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