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| 型號： | GS1582-IBE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | IC,MOT,MC145026P, DIP-16, ENCODER 9 LINE SIMPLEX |
| 中文描述： | 多速率的電纜驅(qū)動器，音頻多路復(fù)用器和ClockCleaner⑩串行 |
| 文件頁數(shù)： | 28/114頁 |
| 文件大小： | 1224K |
| 代理商： | GS1582-IBE3 |
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GS1582 Data Sheet
40117 - 1 November 2007
28 of 114
4.3 SMPTE Mode
The GS1582 operates in SMPTE mode when the SMPTE_BYPASS pin is set
HIGH and the DVB_ASI pin is set LOW.
In this mode, the parallel data will be scrambled according to SMPTE 259M or
292M, and NRZ-to-NRZI encoded prior to serialization.
4.3.1 HVF Timing
In SMPTE mode, the GS1582 can automatically detect the video standard and
generate all internal timing signals. The total line length, active line length, total
number of lines per field/frame and total active lines per field/frame are calculated
for the received parallel video.
When DETECT_TRS is LOW, the video standard and timing signals are based on
the externally supplied H_Blanking, V_Blanking, and F_Digital signals. These
signals go to the H/HSYNC, V/VSYNC and F/DE pins respectively. When
DETECT_TRS is HIGH, the video standard timing signals will be extracted from the
embedded TRS ID words in the parallel input data. Both 8-bit and 10-bit TRS code
words will be identified by the device.
NOTE: IO processing must be enabled for the device to remap 8-bit TRS words to
the corresponding 10-bit value for transmission. See
Section 4.9.4.2
for more
information.
The GS1582 determines the video standard by timing the horizontal and vertical
reference information supplied at the H/HSYNC, V/VSYNC, and F/DE input pins,
or contained in the TRS ID words of the received video data. Therefore, full
synchronization to the received video standard requires one complete video frame.
Once synchronization has been achieved, the GS1582 will continue to monitor the
received TRS timing or the supplied H, V, and F timing information to maintain
synchronization. GS1582 will lose all timing information immediately following loss
of H, V and F.
The H signal timing should also be configured via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line based blanking or TRS based
blanking. See
Packet Generation and Insertion on page 68
.
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H input should be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words. This is the default H timing used by the
device.
The timing of these signals is shown in
Figure 4-2
.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| GS-158N | 制造商:Taiyo Electric Ind. 功能描述: |
| GS15A | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop |
| GS15A/B | 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS15A/B-2P1J | 制造商:Mean Well 功能描述: |
| GS15A/B-6P1J | 制造商:Mean Well 功能描述: |
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