19-4750; Rev 1; 07/11 102 of 194 B. Field Name Addr (A:) Bit [x:y] Type Description CWCDIE [95:88] [7:0] rwc-_-i" />
參數(shù)資料
型號(hào)： DS34S132GN+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 5/194頁(yè)
文件大?。?/td> 0K
描述： IC TDM OVER PACKET 676-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
功能： TDM-over-Packet（TDMoP）
接口： TDMoP
電路數(shù)： 1
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-PBGA（27x27）
包裝： 管件
其它名稱： 90-34S13+2N0
DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
102 of 194
B. Field
Name
Addr (A:)
Bit [x:y] Type
Description
CWCDIE
[95:88]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G11SRL[z] = 1 and B.G11SRIE[z] = 1, forces G.GSR5[11] = 1.
G12SRIE. A:01B0h
Group 12 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[103:96]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G12SRL[z] = 1 and B.G12SRIE[z] = 1, forces G.GSR5[12] = 1.
G13SRIE. A:01B4h
Group 13 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[111:104]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G13SRL[z] = 1 and B.G13SRIE[z] = 1, forces G.GSR5[13] = 1.
G14SRIE. A:01B8h
Group 14 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[119:112]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G14SRL[z] = 1 and B.G14SRIE[z] = 1, forces G.GSR5[14] = 1.
G15SRIE. A:01BCh
Group 15 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[127:120]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G15SRL[z] = 1 and B.G15SRIE[z] = 1, forces G.GSR5[15] = 1.
G16SRIE. A:01C0h
Group 16 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[135:128]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G16SRL[z] = 1 and B.G16SRIE[z] = 1, forces G.GSR5[16] = 1.
G17SRIE. A:01C4h
Group 17 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[143:136]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G17SRL[z] = 1 and B.G17SRIE[z] = 1, forces G.GSR5[17] = 1.
G18SRIE. A:01C8h
Group 18 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[151:144]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G18SRL[z] = 1 and B.G18SRIE[z] = 1, forces G.GSR5[18] = 1.
G19SRIE. A:01CCh
Group 19 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[159:152]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G19SRL[z] = 1 and B.G19SRIE[z] = 1, forces G.GSR5[19] = 1.
G20SRIE. A:01D0h
Group 20 Status Register Interrupt Enable.
RSVD
[31:8]
Reserved.
CWCDIE
[167:160]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G20SRL[z] = 1 and B.G20SRIE[z] = 1, forces G.GSR5[20] = 1.
G21SRIE. A:01D4h
Group 21 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
CWCDIE
[175:168]
[7:0] rwc-_-i3
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G21SRL[z] = 1 and B.G21SRIE[z] = 1, forces G.GSR5[21] = 1.
G22SRIE. A:01D8h
Group 22 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
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