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參數(shù)資料
| 型號： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 128/194頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
39 of 194
Figure 9-13. TSA Block Environment
DS34S132
TXP TSA
RXP TSA
Rcv TDM
Port
Xmt TDM
Port
Bundle Loopback
TDM Port Line &
Timeslot Loopbacks
TXP SAT/CES Engines
TXP HDLC Engines
RXP HDLC Engines
RXP SAT/CES Engines
Xmt CAS
Monitor
TXP CAS
Monitor
TXP SW
CAS
Xmt SW
CAS
TXP Cond
Data
Xmt Cond
Data
One Timeslot Assigner circuit is provided for each TDM Port and in each direction so that any combination of
timeslots from a TDM Port can be assigned to a Bundle. The ordering of the data within a packet always follows the
“chronological” order on the T1/E1 line. For example if Timeslots 0, 7, 13 and 17 are assigned to Bundle A, the data
in the packet payload section will be 0, 7, 13, 17, 0, 7, 13, 17 and so on. The timeslot order cannot be programmed
to provide an ordering like 7, 0, 17, 13.
For Structured TDM data streams, the association between a Bundle to its TDM Port number and T1/E1 Timeslot
positions is programmed using B.BCDR4.PNS, B.BCDR2.ATSS and TSAn.m. To function properly, every Bundle
must be assigned at least one TDM Port Timeslot and each TDM Port Timeslot cannot be assigned to more than
one Bundle. Timeslots can be ignored by not assigning them to Bundles.
Unstructured TDM data streams do not provide a means to byte-align to the data stream. The Timeslots are viewed
by the S132 as 8–bit time periods that are not synchronized to a framing pattern, but timed to a 125 us time period.
Unstructured Bundles use the entire TDM Port bandwidth. The first Timeslot (TS0) of the TDM Port must be
assigned to the Unstructured Bundle using the B.BCDR4.PNS, B.BCDR2.ATSS and TSAn.m registers. The first
Timeslot is the only Timeslot that is assigned to that Bundle and no other Timeslots on that TDM Port should be
assigned/enabled. Although the T1 line rate includes a non-integer number of bytes within a 125 us period (193
bits), there are no register settings to include/assign the 193rd bit. An Unstructured TDM Port that is programmed
with Pn.PTCR1.BPF = Pn.PRCR1.BPF = 0x17 can support both 192 and 193 bits per 125 us time period.
Although the packets for Clock Only Bundles do not include packet payload (no Timeslot data), the S132 requires
that Clock Only Bundles must also be assigned a fraction/portion of the TDM Port bandwidth (assigned 1 or more
Timeslots). Assigning one Timeslot to a Clock Only Bundle allocates enough processing time (from the TDM Port)
for the S132 to perform the Clock Only Bundle functions. A Timeslot that is assigned to a Clock Only Bundle cannot
be assigned to any other Bundle even though the payload data is not used (the Timeslot processing time period
can only be used by one Bundle). For E1-CES Timeslot 0 can be used for a Clock Only Bundle since the Framing
Timeslot is not normally carried in the PW packets. For T1-CES, T1-SAT and E1-SAT, two TDM Ports (out of the
32 TDM Ports) can be connected in “parallel” so that one TDM Port is used for the Clock Only Bundles and the
other TDM Port is used for the Bundle with payload data. The use of Clock Only Bundles is optional to provide a
technique to reduce the packet latency through the use of smaller packets with high priority scheduling.
The outgoing CAS codes can be monitored in both directions. The Xmt CAS codes (RXP direction) can be read
using Pn.PRSR1 – Pn.PRSR4. The TXP CAS codes can be read using Pn.PTSR1 – Pn.PTSR4. The receive TDM
Port CAS codes can be sourced from RSIG or RDAT (Pn.PRCR1.CS). The CAS codes can be monitored by polling
the Monitor registers (PRSRx and PTSRx) or by using an interrupt hierarchy that reports when a CAS change has
been detected (G.GSR2 and G.GSR3). The interrupt method is also described in the “Interrupt Hierarchy” section.
In the RXP direction, when CAS Signaling is enabled on a Bundle (B.BCDR4.RXBTS = 2), the CAS codes received
from RXP packets are forwarded to the TDM Port and transmitted in the proper Timeslot CAS code positions.
When RXP CAS codes are received they are first stored in a Jitter Buffer along with the CES Bundle payload data
to smooth out the irregular (bursty) receive packet rate. If the RXP packet stream is blocked (e.g. for a fault), the
S132 will continue to send CAS codes until the Jitter Buffer is empty. When the Jitter Buffer empties, the S132 can
be programmed to continue sending the last stored CAS code or to send the programmed Xmt SW CAS
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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