19-4750; Rev 1; 07/11 68 of 194 The EMA.WSR1,
參數(shù)資料
型號(hào): DS34S132GN+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 160/194頁(yè)
文件大小: 0K
描述: IC TDM OVER PACKET 676-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
功能: TDM-over-Packet(TDMoP)
接口: TDMoP
電路數(shù): 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-PBGA(27x27)
包裝: 管件
其它名稱: 90-34S13+2N0
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
68 of 194
The EMA.WSR1, EMA.WSR2, EMA.WSRL1 and EMA.WSRIE1 registers provide other control and status bits for
the TXP CPU FIFO and the SDRAM TXP CPU Queue.
9.5 Clock Recovery Functions
The S132 includes a DSP to implement its Clock Recovery functions. The Clock Recovery functions include the
RXP and TXP PW-Timing functions. The DSP is controlled by firmware code. The firmware code must be
downloaded to the S132 each time a global reset is initiated (e.g. after power up). In addition to the firmware code,
the Clock Recovery functions must be programmed using the CR. Registers. The CR. Registers enable the PW-
Timing functions to be configured according to each PW application (e.g. DCR-DT vs. ACR). The functionality of
the firmware and its configuration registers is defined in an independent S132 Firmware Definition document.
9.6 Miscellaneous Global Functions
9.6.1 Global Resets
A Global Reset can be implemented using G.GRCR.RST or the RST_N pin.
9.6.2 Latched Status and Counter Register Reset
The S132 provides Latched Status register bits so that the CPU can discover transient events that might otherwise
be missed by a simple “real-time” status register. Programming the G.GCR.LSBCRE register selects whether to
clear (restore to the default value) the Latched Status bits automatically when the CPU Reads the Latched Status
register, or to wait until the CPU performs an explicit Write operation to over-write the Latched Status value.
The G.GCR.CCOR bit selects whether the “Clear on Read” function is enabled for the RXP Bundle Counts, TXP
Bundle Counts and Packet Classifier Counts or whether the “Clear on Read” function for these registers is disabled
(the counters roll over after they reach their maximum value).
9.6.3 Buffer Manager
The Buffer Manager controls and monitors the SDRAM that stores the Bundle and RXP/TXP CPU Queues and the
TXP Header Descriptors. The Buffer Manager environment is depicted in Figure 9-28.
Figure 9-28. Buffer Manager Environment
DS34S132
RXP/TXP
SAT/CES Engines
RXP/TXP
HDLC Engines
TXP Pkt
Generator
HDLC Connections
SAT/CES Connections
RXP Pkt
Classifier
Buffer
Manager
To SDRAM
To external CPU
CPU Connections
The starting addresses for the Queues and TXP Header Descriptor section are programmed using the EMI
registers. Each address is a 16-bit address that indexes a 2 Kbyte segment of SDRAM memory (2^16 x 2 Kbyte = 1
Gbit). For a smaller SDRAM size the address bit-width is reduced (e.g. a 512 Kbit SDRAM uses 15-bit addressing).
The programmed starting addresses are programmed using the following queue depth equations. The “Register
Guide” section provides example settings that can be used in most applications.
RXP CPU Queue:
16384 * maximum # of RXP CPU Packets
TXP CPU Queue:
16384 * maximum # of TXP CPU Packets
TXP Header Descriptors:
1024 * maximum # of BIDs
TXP Bundle Payload Queues:
131072 * maximum # of BIDs
RXP Bundle Jitter Buffer Queues: G.GCR.JBMD setting in Kbytes * maximum # BIDs
Total SDRAM storage area:
sum of all of the above
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