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| 型號(hào)： | DS34S132GN+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 153/194頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
61 of 194
9.3.2.3.11 “CPU Debug RXP PW Bundle” Setting (RXBDS)
PW Bundles (not including OAM Bundles) are normally used for SAT, CES, HDLC or PW-Timing Connections, but
can be programmed to instead send packets to the CPU for debug. When the CPU Debug setting is enabled
(B.BCDR4.RXBDS), the received packets for the RXP Bundle are redirected to the CPU (instead of sending the
data to the SAT/CES/HDLC/Clock Recovery Engines). The RXP Bundle parameters can be fully programmed or
partially programmed. A received packet is identified as a “CPU Debug RXP PW Bundle” packet when the packet
includes any of the PW Header Types, the PW-ID of the packet matches a BID and the Bundle that uses that BID is
programmed to “CPU Debug” (RXBDS). The other Bundle register settings are ignored.
9.3.2.3.12 PW Bundle with Unknown UDP Protocol Type (UPVCE and DPS5)
When the Classifier is programmed to verify the UDP Payload Protocol (PC.CR1.UPVCE) and a UDP packet is
received with a recognized BID, but with a UDP Payload Protocol value that is not equal to PC.CR2.UPVC1 or
UPVC2, PC.CR1.DPS5 selects whether the packet is sent to the CPU (0) or Discarded (1). The DPS5 setting does
not affect packets that are otherwise identified as CPU packets.
9.3.2.3.13 PW Bundle In-band VCCV OAM (RXOICWE and DPS7)
In-band VCCV CPU Connections can be thought of as “secondary” connections that are used to support the
“primary” SAT/CES/HDLC/Clock Only PW for functions like setup, configuration and monitoring. An In-band VCCV
connection can be established before the primary connections have been established. The In-band VCCV may be
used, e.g., to negotiate the configuration settings of the primary connection before enabling the primary connection.
The Classifier monitors for In-band VCCV packets for a Bundle when B.BCDR4.RXOICWE = 1. The PC.CR1.DPS7
setting determines whether In-band VCCV packets are forwarded to the CPU (0) or Discarded (1).
9.3.2.3.14 PW Bundle with Too Many MPLS Labels (DPS10)
When an MFA-8 (MPLS) packet is received with a recognized BID and the packet includes more than 2 MPLS
Labels, PC.CR1.DPS10 determines whether the packet is forwarded to the CPU (0) or Discarded (1).
9.3.2.3.15 PW OAM Bundle - Out-band VCCV OAM Packets (DPS7)
Up to 32 Out-band VCCV OAM Connections can be programmed using OAM BIDs. OAM BIDs are used to support
what the standards call “UDP-specific OAM”, “Out-band VCCV” or “OAM using Separate PW-ID” (meaning OAM
PW-IDs that are separate/unique from the PW-IDs used by the primary PW connection). The UDP application
commonly uses this OAM form instead of the “In-band VCCV” form. This OAM format is not commonly used with
L2TPv3, MEF-8 or MFA-8. A packet is recognized as an OAM Bundle when the received packet includes a one of
the PW Header Types and the received PW-ID matches one of the 32 programmed OAM BIDs. The PC.CR1.DPS7
setting determines whether this packet type is forwarded to the CPU (0) or Discarded (1).
9.3.3 TXP Packet Generation
The TXP Packet Generator schedules the packet data for CPU, PW-Timing, HDLC and SAT/CES Payload
Connections and appends the TXP Header (including FCS field values when required) and TXP Timestamp (when
required). The Ethernet FCS is appended outside this block in the Ethernet MAC block.
Figure 9-24. TXP Packet Generation Environment
DS34S132
Ethernet
MAC
SAT/CES Connection
HDLC Connection
TXP Timing Connection
TXP SAT/CES Payload data from
Buffer Manager
TXP HDLC Payload data from
Buffer Manager
TXP RTP Timestamp
information from Buffer Manager
TXP Pkt
Scheduling &
Generation
RXP CPU Queue packets from Buffer Manager
CPU Connection
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類(lèi)型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類(lèi)型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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