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| 型號： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 133/194頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
43 of 194
a Bundle is equivalent to enabling a “Connection” for that Engine (e.g. enabling SAT/CES Engine = enable
SAT/CES Connection). B.BCDR1.RXBDS further supplements these selections by providing the ability to instead
forward the packets for a Bundle to the CPU (for debug; CPU Debug RXP PW Bundle) or to discard the packet
payload for Clock Only Bundles (to reduce the S132 payload processing functions). The following types of Bundles
can be programmed using these registers. The “Register Definition” and the “Register Guide” sections provide
more information on how to set these registers for each Bundle type.
SAT
Nx64 CES without CAS
Nx64 CES with CAS
HDLC for Unstructured TDM Port
Structured Nx64 HDLC
Structured 56 Kb/s or 16 Kb/s HDLC
SAT Clock Only
CES Clock Only
The SAT and CES Bundles can include an RXP PW-Timing Connection by enabling B.BCDR4.PCRE and/or a TXP
PW-Timing Connection by including the RTP Timestamp in the TXP Header Descriptor for that Bundle (see the
“TXP SAT/CES and HDLC PW Packet Generation” section). The Clock Recovery functions are described in more
detail in the “PW-Timing” section.
All of the Bundle types can include support for In-band VCCV (In-band VCCV CPU Connection). When a packet is
received for a recognized Bundle, the received packet header matches the In-band VCCV Control Word
(PC.CR5.VOV and PC.CR5.VOM) and In-band VCCV has been enabled for that Bundle (B.BCDR4.RXCWE and
B.BCDR4.RXOICWE) the S132 forwards the In-band VCCV packet to the CPU or discards the packet according to
the PC.CR1.DPS7 setting (OAM Packet Discard switch; this switch also affects other OAM types).
In the TXP direction, Receive TDM Port data that is ready for transmission is buffered in one of two priority queues
so that the packets can be scheduled according to their importance when congestion occurs. TXP Packets that are
buffered in the higher priority queue are processed before TXP Packets in the lower priority queue. For example,
Bundles with PW-Timing Connections can be assigned to the higher priority queue. The TXP priority is selected for
each TXP Bundle using B.BCDR3.TXBPS.
9.2.5.1 HDLC Engine
The S132 includes 256 HDLC Engines, one each for up to 256 Bundles. Several HDLC Bundle types are supported
including Unstructured HDLC (full TDM Port bandwidth), Structured Nx64 Kb/s HDLC, Structured 56 Kb/s or
Structured 16 Kb/s. With HDLC Bundles the terms “Unstructured” and “Structured” refer to the format of the TDM
Port. These terms do not have any direct relevance to the packet format of an HDLC Bundle. A single Structured
TDM Port can support any combination of Structured HDLC Bundles and CES Bundles since each Bundle can be
assigned to independent Timeslots on a Structured TDM Port.
Figure 9-14. HDLC Engine Environment
DS34S132
TXP
TSA
RXP
TSA
TXP HDLC Engine
RXP HDLC Engine
Buffer
Manager
HDLC
Connection
An Unstructured HDLC Bundle uses the entire bandwidth of its assigned TDM Port. The HDLC coding/decoding is
performed using the entire data stream without regard for T1/E1 framing or Timeslot positions.
Structured HDLC Bundles can be programmed to use 2-bit, 7-bit or 8-bit HDLC coding (for 16 Kb/s, 56 Kb/s and
“Nx64 Kb/s” channels respectively; B.BCDR1.SCTXCOS). The bit-width setting identifies how many bits are used in
the assigned Timeslot. For 8-bit, all 8 bits of the timeslot are HDLC coded. For 7-bit coding, only the 7 MSbits are
HDLC coded (the LSbit is unused). For 2-bit coding, the two MSbits or two LSbits can be selected for HDLC coding
(the remaining 6-bits are unused). Unstructured HDLC Bundles always use 8-bit coding.
The “8-bit” format allows an HDLC Bundle to combine the data from multiple 8-bit Timeslots of a single Structured
T1/E1 to support bandwidths like 384 Kb/s (using six 8-bit Timeslots). Any number of 8-bit Timeslots can be
combined (up to 24 for Structured T1 or 31 for Structured E1).
Only one 2-bit or 7-bit HDLC coded Timeslot from a Structured T1/E1 can be assigned to an HDLC Bundle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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