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參數(shù)資料
| 型號： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 82/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Data Communication Modes Functional Description
AMD
4–30
nization at the receiver may take longer because the first transition seen on the TxD pin
may not coincide with a bit boundary.
Note that in order for this to function properly, bits D3 and D2 of WR10 must be set to ‘1’
and ‘0’ respectively.
4.9
The SCC supports SDLC Loop mode in addition to normal SDLC. SDLC Loop mode is
very similar to normal SDLC. It is usually used in applications where a point-to-point net-
work is not appropriate (for example, point-of-sale terminals).
S DLC LOOP MODE
In an SDLC Loop there is a primary station, called the controller, that manages the mes-
sage traffic flow on the loop. SDLC Loop is a special type of configuration in which one or
more stations are connected in a serial fashion; each station is a repeater of the up-loop
data to the next down-loop station.
SDLC loop operation requires the transmission link operate in a half-duplex, one direction
only, mode. Data transmitted on the loop by the primary station are relayed from station
to station.
4.9.1
There are certain restrictions as to when and how a secondary station physically be-
comes part of the loop. A secondary station that has just powered up must monitor the
loop, without the one-bit-time delay, until it recognizes an EOP. While waiting for an EOP,
the SCC ties TxD to RxD with only the internal gate delays in the signal path. When the
first EOP is recognized by the SCC, the BREAK/ABORT status bit is set in RR0, generat-
ing an External/Status interrupt (if so enabled). At the same time, the On-Loop bit in
RR10 (D4) is set to indicate that the SCC is indeed on-loop, and a one-bit time delay is
inserted in the TxD to the RxD patch. This does not disturb the loop because the line is
marking idle between the time that the controller sends the EOP and the time that it re-
ceives the EOP back. The secondary station that has gone on-loop cannot transmit a
message until a flag and the next EOP are received. The requirement that a flag be re-
ceived ensures that the SCC cannot erroneously send messages until the controller ends
the current polling sequence and starts another one. A secondary station goes off\loop in
a similar manner.
Going On Loop
1
1
0
0
1
1
1
1
1
1
0
0
Transmitter Disabled Here
TxD Pin Output (NRZI Encoded)
High
Low
10216A-019A
Figure 4–19. Transmitter Disabling with NRZI Encoding
A secondary station in an SDLC Loop is always listening to the messages being sent
around the loop and must pass these messages to the rest of the loop by re-transmitting
them with a one-bit-time delay. When given a command to go off-loop, the secondary sta-
tion waits until the next EOP to remove the one-bit-time delay.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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