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| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 66/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Data Communication Modes Functional Description
AMD
4–14
4.7
4.7.1
Receiver operation in SDLC mode begins in a Hunt mode where the communications line
is monitored for a synchronizing pattern on a bit-by-bit basis. The receiver may be placed
in Hunt mode by having the processor issue the Enter Hunt Mode command via bit D4 in
WR3, but will always start out in Hunt mode when it is enabled. The Enter Hunt Mode bit
in WR3 is a command so writing a ‘0’ to it has no effect.
S DLC MODE OPERAT ION
Rec eiver Operation
The Hunt status of the receiver is reported by the SYNC/HUNT status bit in RR0. InSDLC
mode, this status bit will be set to ‘1’ when either; 1) the processor issues the Enter Hunt
Mode command, 2) the processor disables the receiver, or 3) an abort is detected. It will
be reset to ‘0’ when the receiver leaves Hunt mode, or when the abort condition goes
away. Unlike BISYNC or MONOSYNC mode, once the SYNC/HUNT status bit is reset it
does not need to be set again in between frames because the Receiver always maintains
synchronization.
This SYNC/HUNT status bit is one of the possible sources of External/Status interrupts,
with both transitions causing an interrupt. This is true even if the SYNC/HUNT bit is set as
a result of the processor issuing the Enter Hunt Mode command.
While in Hunt mode the Receive SYNC Register and WR7 are used in establishing char-
acter synchronization. As data are received, the receiver searches for the bit pattern,
‘01111110’, programmed in WR7. This sequence of six consecutive ‘1’ bits is prevented
from occurring randomly elsewhere in the frame through a process called zero-bit inser-
tion in which the transmitter inserts a ‘0’ bit after five consecutive ‘1’ bits, irrespective of
character boundaries. In turn, the receiver always searches the receive data stream on a
bit-by-bit basis for five consecutive ‘1’s. When the receiver detects a ‘0’ bit followed by
five ‘1’ bits, it inspects the following bit. If it is a ‘0’, the one bits are passed as data and
the zero bit is deleted. If the sixth bit is a ‘1’, the receiver inspects the seventh bit. If it is a
‘0’, a flag has been encountered and the receiver is synchronized to that flag; if it is a ‘1’
an abort or an EOP (End of Poll) has been encountered.
When a flag is detected and Address Search mode is not enabled, the receiver leaves
Hunt mode and character assembly begins with the first non-flag character. Once charac-
ter assembly begins characters are assembled according to the number of bits per char-
acter specified until: 1) an end of frame flag is detected, 2) an abort pattern is detected, 3)
the receiver is disabled, or 4) a channel or hardware reset is executed.
All data passes through the Receive Sync Register and the 3-bit delay before entering the
Receive Shift Register once synchronization is achieved. Ordinarily, the receiver transfers
all data between flags to the Receive Data FIFO, but while it is in Hunt mode no flags will
be transferred.
4.7.1.1
In SDLC mode, if bit D7 of WR11 is set to ‘0’, the SYNC pin will be configured as an out-
put and the SCC will drive it Low every time a flag pattern is detected in the data stream.
The timing for the SYNC signal is shown in Figure 4–11.
Flag Detect Output
4.7.1.2
The initialization sequence for the receiver in SDLC mode is: WR4 first, to select the
mode, then WR10 to modify it if necessary, WR6 to program the address, WR7 to pro-
gram the flag and WR3 and WR5 to select the various options. At this point the other reg-
isters should be initialized as necessary. When all of this is complete, the receiver may be
enabled by setting bit D0 of WR3 to ‘1’.
Receiver Initialization
4.7.1.3
In addition to the 8-bit Receive Data and Error FIFO’s, the CMOS SCC Receiver incorpo-
rates a 14-bit receive byte counter and a 10x19-bit FIFO array for storing frame status for
up to ten frames. This FIFO enhances the SCC’s ability to receive high speed back-to-
10x19-Bit Frame Status FIFO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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