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參數(shù)資料
| 型號： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 138/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Register Description
AMD
6–28
Enter Search Mode (001)
. Issuing this command causes the DPLL to enter the Search
mode, where the DPLL searches for a locking edge in the incoming data stream. The ac-
tion taken by the DPLL upon receipt of this command depends on the operating mode of
the DPLL.
In NRZI mode, the output of the DPLL is High while the DPLL is waiting for an edge in the
incoming data stream. After the Search mode is entered, the first edge the DPLL sees is
assumed to be a valid data edge, and the DPLL begins the clock recovery operation from
that point. The DPLL clock rate must be 32 times the data rate in NRZI mode. Upon leav-
ing the Search mode, the first sampling edge of the DPLL occurs 16 of these 32X clocks
after the first data edge and the second sampling edge occurs 48 of these 32X clocks
after the first data edge. Beyond this point, the DPLL begins normal operation, adjusting
the output to remain in sync with the incoming data.
In FM mode, the output of the DPLL is Low while the DPLL is waiting for an edge in the
incoming data stream. The first edge the DPLL detects is assumed to be a valid clock
edge. For this to be the case, the line must contain only clock edges; i.e., with FM1 en-
coding, the line must be continuous ‘0’s. With FM0 encoding the line must be continuous
‘1’s, whereas Manchester encoding requires alternating ‘1’s and ‘0’s on the line. The
DPLL clock rate must be 16 times the data rate in FM mode. The DPLL output causes the
receiver to sample the data stream in the nominal center of the two halves of the bit cell
to decide whether the data was a ‘1’ or a ‘0’. After this command is issued, as in NRZI
mode, the DPLL starts sampling immediately after the first edge is detected. (In FM
mode, the DPLL examines the clock edge of every other bit cell to decide what correction
must be made to remain in sync.) If the DPLL does not see an edge during the expected
window, the one clock missing bit in RR10 is set. If the DPLL does not see an edge after
two successive attempts, the two clocks missing bit in RR10 is set and the DPLL auto-
matically enters the Search mode. This command resets both clock missing latches.
Reset Clock Missing (010)
. Issuing this command disables the DPLL, resets the clock
missing latches in RR10, and forces a continuous Search mode state.
Disable DPLL (011)
. Issuing this command disables the DPLL, resets the clock missing
latches in RR10, and forces a continuous Search mode state.
Set Source = BR Gen (100)
. Issuing this command forces the clock for the DPLL to
come from the output of the baud rate generator.
Set Source =
RTxC
(101)
. Issuing this command forces the clock for the DPLL to come
from the
RTxC
pin or the crystal oscillator, depending on the state of the XTAL/no XTAL
bit in WR11. This mode is selected by a channel or hardware reset.
Set FM Mode (110)
. This command forces the DPLL to operate in the FM mode and is
used to recover the clock from FM or Manchester-encoded data. (Manchester is decoded
by placing the receiver in NRZ mode while the DPLL is in FM mode.)
Set NRZI Mode (111)
. Issuing this command forces the DPLL to operate in the NRZI
mode. This mode is also selected by a hardware or channel reset.
Bit 4: Local Loopback
Setting this bit to ‘1’ selects the Local Loopback mode of operation In this mode, the in-
ternal transmitted data are routed back to the receiver, as well as to the
TxD
pin. The
CTS
and
DCD
inputs are ignored as enables in Local Loopback mode, even if Auto En-
ables is selected. (if so programmed, transitions on these inputs still cause interrupts.)
This mode works with any Transmit/Receive mode except Loop mode. For meaningful
results, the frequency of the transmit and receive clocks must be the same. This bit is re-
set by a channel or hardware reset.
Bit 3: Auto Echo
Setting this bit to ‘1’ selects the Auto Enable mode of operation. In this mode, the TxD
pin is connected to RxD, as in Local Loopback mode, but the receiver still listens to the
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| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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