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| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 46/194頁(yè) |
| 文件大小： | 797K |
| 代理商： | AM8530H |
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I/O Programming Functional Description
AMD
3–15
3.8.4
The Tx Underrun/EOM status bit is used in SDLC and Synchronous modes of operation
to control the transmission of CRC characters. This bit is set to ‘1’ when the Transmit
Buffer and Transmit Shift Register go empty and is reset to ‘0’ by issuing the Reset
Transmit Underrun/EOM command in WR0. Only the Low-to-High transition of this bit will
cause the latches to close and, if the Tx Underrun/EOM IE bit in WR15 (D6) is set to ‘1’,
cause an External/Status Interrupt to be generated.
T x Underrun/EOM
This status bit is always set to ‘1’ in Asynchronous mode unless a Reset Transmit Under-
run/EOM command is erroneously issued. In this case, the Send Abort Command can be
used to set this bit to ‘1’ and, at the same time, cause an External/Status Interrupt.
Note that this bit will be set to ‘1’ when either of the following occurs; 1) a Send Abort
command is issued, 2) the transmitter is disabled, or 3) a Channel or Hardware Reset is
executed.
3.8.5
The
CTS
Status bit reports the state of the
CTS
input pin the last time any of the enabled
External/Status bits changed. Any transition on the
CTS
pin, while no other interrupts are
pending, latches the state of the
CTS
pin and generates an External/Status interrupt if the
CTS
IE bit in WR15 is set to ‘1’. However, only an odd number of transitions on the
CTS
pin while another External/Status is pending will cause an External/Status interrupt after
the Reset External/Status Interrupt command is issued.
Clear to S end
If the
CTS
IE bit is reset, the
CTS
status merely reports the current inverted unlatched
state of the
CTS
pin; that is, if the
CTS
pin is Low, the
CTS
status bit will be High.
Note that after the Reset External/Status Interrupt command is issued, if the latches were
closed, they will close again if there was an odd number of transitions on the
CTS
pin;
they will remain open if there was an even number of transitions on the input pin.
3.8.6
The DCD Status bit reports the state of the
DCD
input pin the last time any of the enabled
External/Status bits changed. Any transition on the
DCD
pin, while no other interrupts are
pending, latches the state of the
DCD
pin and generates an External/Status interrupt if
the DCD IE bit in WR15 is set to ‘1’. However, only an odd number of transitions on the
DCD
pin while another External/Status is pending will cause an External/Status interrupt
after the Reset External/Status Interrupt command is issued.
Data Carrier Detec t
If the DCD IE bit is reset, the DCD status merely reports the current inverted unlatched
state of the DCD pin; that is, if the
DCD
pin is Low, the DCD status bit will be High.
Note that after the Reset External/Status Interrupt command is issued, if the latches were
closed, they will close again if there was an odd number of transitions on the
DCD
pin;
they will remain open if there was an even number of transitions on the input pin.
If careful attention is paid to details, the interrupt service routine for External/Status inter-
rupts is straightforward. To determine which bit or bits changed state, the routine should
first read RR0 and compare it to a copy from memory. For each changed bit, the appro-
priate action should be taken and the copy in memory updated. The service routine
should close with a Reset External/Status Interrupts command to re-open the latches.
The copy of RR0 in memory should always have the Zero Count bit set to ‘0’, since this
will be the state of the bit after the Reset External/Status Interrupts command at the end
of the service routine.
3.9
The SCC offers several alternatives for the block transfer of data. The various options are
selected via WR1 and WR14 as follows.
BLOCK T RANS FERS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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