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參數(shù)資料
| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 142/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Register Description
AMD
6–32
The XTAL oscillator should not be selected in External Sync mode.
In Asynchronous mode, the operation of this bit is identical to that of the CTS status bit,
except that this bit reports the state of the
SYNC
pin.
In External sync mode the
SYNC
pin is used by external logic to signal character syn-
chronization. When the Enter Hunt Mode command is issued in External Sync mode, the
SYNC pin must be held High by external sync logic until character synchronization is
achieved. A High on the
SYNC
pin holds the Sync/Hunt bit in the reset condition.
When external synchronization is achieved,
SYNC
must be driven Low on the second
rising edge of the Receive Clock after the last rising edge of the Receive Clock on which
the last bit of the receive character was received. Once
SYNC
is forced Low, it is good
practice to keep it Low until the CPU informs the external sync logic that synchronization
has been lost or that a new message is about to start. Both transitions on the
SYNC
pin
case External/Status interrupts if the Sync/Hunt IE bit is set to ‘1’.
The Enter Hunt Mode command should be issued whenever character synchronization is
lost. At the same time, the CPU should inform the external logic that character synchroni-
zation has been lost and that the SCC is waiting for SYNC to become active.
In the Monosync and Bisync Receive modes, the Sync/Hunt status bit is initially set to ‘1’
by the Enter Hunt Mode command. The Sync/Hunt bit is reset when the SCC establishes
character synchronization. Both transitions cause External/Status interrupts if the Sync/
Hunt IE bit is set when the CPU detects the end of message or the loss of character syn-
chronization. When the CPU detects the end of message of the loss of character
synchronization, the Enter Hunt Mode command should be issued to set the Sync/Hunt
bit and cause an External/Status interrupt. In this mode, the
SYNC
pin is an output, which
goes Low every time a sync pattern is detected in the data stream.
In the SDLC modes, the Sync/Hunt bit is initially set by the Enter Hunt Mode command or
when the receiver is disabled. It is reset when the opening flag of the first frame is de-
tected by the SCC. An External/Status interrupt is also generated if the Sync/Hunt IE bit is
set. Unlike the Monosync and Bisync modes, once the Sync/Hunt bit is reset in SDLC
mode, it does not need to be set when the end of the frame is detected. The SCC auto-
matically maintains synchronization. The only way the Sync/Hunt bit can be set again is
by the Enter Hunt Mode command or by disabling the receiver.
Bit 3: Data Carrier Detect
If the DCD IE bit in WR 15 is set, this bit indicates the state of the
DCD
pin the last time
the Enabled External/Status bits changed. Any transition on the
DCD
pin while no inter-
rupt is pending latches the state of the
DCD
pin and generates an External/Status inter-
rupt. Any odd number of transitions on the
DCD
pin while another External/Status
interrupt is pending also causes an External/Status interrupt condition. If the DCD IE is
reset, this bit merely reports the current, unlatched state of the
DCD
pin.
Bit 2: TX Buffer Empty
This bit is set to ‘1’ when the transmit buffer is empty. It is reset while CRC is sent in a
synchronous or SDLC mode and while the transmit buffer is full. The bit is reset when a
character is loaded into the transmit buffer. This bit is always in the set condition after a
hardware or channel reset.
Bit 1: Zero Count
If the Zero Count Interrupt Enable bit is set in WR15, this bit is set to one while the
counter in the baud rate generator is at the count zero. If there is no other External/Status
interrupt condition pending at the time this bit is set, an External/Status interrupt is gener-
ated. However, if there is another External/Status interrupt pending at this time, no inter-
rupt is initiated until interrupt service is complete. If the Zero Count condition does not
persist beyond the end of the interrupt service routine, no interrupt will be generated. This
bit is not latched High, even though the other External/Status latches close as a result of
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PDF描述 |
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| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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