- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366552 > AM8530H (Advanced Micro Devices, Inc.) Serial Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 79/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)當(dāng)前第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)
Data Communication Modes Functional Description
AMD
4–27
4.8
In SDLC Modes, the transmitter automatically envelopes the data written to the Transmit
Buffer Register (WR8) with the flag character in WR7. Because the SCC transfers the flag
character eight bits at a time, zero-suppressed flags (i.e., where the ending zero bit of
one flag is the beginning zero bit of the succeeding flag) are not supported. The receiver,
however, can receive either zero-suppressed or fully-formed flags. While flags are trans-
mitted the zero insertion logic is inhibited.
T RANS MIT T ER OPERAT ION
When transmitting data in SDLC modes, note that all data passes through the zero inser-
ter, which adds an extra five bit times of delay between the Transmit Shift Register and
the Transmit Data (TxD) pin.
4.8.1
The initialization sequence for the transmitter in SDLC modes is: WR4 first, to select the
mode, then WR10 to modify it if necessary, WR7 and WR6 to program the flag and ad-
dress field (if used), and then WR3 and WR5 to select the various options. At this point,
the other registers should be initialized as necessary. Once all of this is complete the
transmitter will be idle with the TxD pin pulled high until the transmitter is enabled via bit
D3 in WR5. When this bit is set to ‘1’, the transmitter starts mark idling (i.e., a pattern of
all one bits are sent eight bits at a time), and continues to mark idle until the MARK/FLAG
Idle bit in WR10 (D3) is set to ‘0’. When this bit is reset to ‘0’ and the current mark idle
pattern has left the Transmit Shift Register, the transmitter will begin sending flag charac-
ters and will continue to send flag characters until a character is written to the Transmit
Buffer. During this flag idle time the CRC generator may be initialized by issuing the Re-
set Tx CRC Generator Command in WR0.
T ransmitter Initialization
When a character is written to WR8 and the current flag character has been sent, the
transmitter starts sending data and continues to send data until an underrun condition
occurs. The Tx Buffer Empty status bit in RR0 (D2) will be set to ‘1’ each time the con-
tents of WR8 are transferred to the Transmit Shift Register. It will be reset to ‘0’ each time
the Transmit Buffer is written to, and while the CRC is being sent in SDLC and Synchro-
nous modes. If the Transmitter Interrupt Enable bit in WR1 is set to ‘1’ then the Low-to-
High transition of the Tx Buffer Empty status bit will generate an interrupt.
4.8.2
The Transmitter may be programmed to either mark or flag idle when no data are being
transmitted. If the MARK/FLAG idle bit in WR10 (D3) is set to ‘1’, the transmitter will mark
idle by transmitting continuous ‘1’s; otherwise, it will flag idle by transmitting continuous
flags. The state of this bit determines the idle pattern transmitted after the closing flag of
the frame is sent and not before.
MARK /FLAG Idle Generation
On the NMOS SCC, if the transmitter is actively mark idling, and a frame of data is ready
to be transmitted, the MARK/FLAG idle bit must be set to ‘0’ before data are written to
WR8; otherwise, the opening flag will not be sent properly. However, care must be exer-
cised in doing this because the mark idle pattern (eight ‘1’ bits) is transmitted eight bits at
a time, and all eight bits must have transferred from the Transmit Shift Register before a
flag may be loaded and sent. If data are written into the Transmit Buffer (WR8) before the
flag is loaded into the Transmit Shift Register, the data character written to WR8 will su-
persede flag transmission and the opening flag will not be transmitted.
4.8.3
On the CMOS SCC, if bit D0 of WR15 is set to ‘1’, and the SCC is programmed for SDLC
operation, an option is provided via bit D0 of WR7’ that eliminates this requirement. If bit
D0 of WR7’ is set to ‘1’ and a character is written to the Transmit Buffer while the Trans-
mitter is mark idling, the Mark/Flag Idle bit in WR10 need not be reset to ‘0’ in order to
have the opening flag sent because the transmitter will automatically send it before com-
mencing to send data.
Auto Flag Mode
In addition, as long as bit D0 of WR15 and bit D1 of WR7’ are set to ‘1’, the CRC transmit
generator will be automatically preset to the initial state programmed by bit D7 of WR10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。