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參數(shù)資料
| 型號： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 56/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Data Communication Modes Functional Description
AMD
4–4
4.2.2
Synchronous transmission requires that clocking information be transmitted along with
the data, either by a method of encoding data that contains clocking information, or by a
modem that encodes clock information in the modulation process. In either case, data are
sent at a defined rate which is controlled by a timing source at the transmitter.
S ync hronous T ransmission
Synchronous communication channels send data faster with less overhead than asyn-
chronous channels but are more expensive to design than asynchronous channels. In
synchronous communication, a timing reference, or “clock”, is used to control the transfer
of information. This clock specifies to the receiver when to sample the data (bit synchroni-
zation) in order to ascertain which data value (‘0’ or ‘1’) was transmitted. The optimum
sample times usually correspond to the middle of the bit cell to minimize error. This clock
signal is encoded along with the data sent so the receiver must be able to decode the
Figure 4–1. Asynchronous Format incoming clock signal. A circuit called a “phase-locked
loop” is typically used for this purpose.
In addition, since data rates are usually higher and data are typically sent with no gaps
between characters, synchronous communication requires some level of buffering at both
the transmitter and receiver.
Once bit synchronization has been established, the next phase for the receiver is to know
what group of bits constitute a character (character synchronization). This requires that
the receiver search the receive bit stream on a bit-by-bit basis for a character synchroniz-
ing pattern in order to determine which set of bits in the bit stream defines the first char-
acter transmitted.
Synchronous communication channels are found in many mainframe data networks. The
greater throughput of the synchronous channel is required in mainframe environments
where many terminals are connected to the computer and multiplexed onto one channel.
The synchronous protocols used may be either character-oriented or bit-oriented.
4.2.2.1
In a Character-Oriented Protocol (COP) data are transmitted in message blocks and re-
quire that each block be preceded by either an 8- or 16-bit predefined “sync character”.
In addition, COPs are typically restricted to half-duplex operation and depend heavily on
special control characters or character sequences, such as SOH or DLE STX and ETX, to
determine the start and end of a particular field within a message block. IBM BISYNC is
an example of a COP. MONOSYNC, on the other hand, is a character count protocol
where both ends of the communication link keep track of the number of characters sent
and received. This solves the problem of having to use special control characters for field
delineation as used in the BISYNC protocol. The DDCMP (Digital Data Communication
Message Protocol) from DEC is another example of a character count protocol in use to-
day. MONOSYNC and BISYNC message formats are shown in Figures 4–2 and 4–3, re-
spectively.
Synchronous Character-Oriented Protocol
Since sync characters are only appended to the start of a message block, additional sync
characters may be inserted within a transmission at distinct time intervals or during a
pause in order to maintain synchronization.
4.2.2.2
Bit-Oriented Protocols (BOP) may be used in half- or full-duplex operation and are less
dependent on special control characters. BOPs rely instead on the position of bits within
specific fields.
Synchronous Bit-Oriented
The most common BOPs in use today are High-Level Data Link Control (HDLC) and Syn-
chronous Data Link Control (SDLC). These two protocols are nearly identical except for
minor differences in the use of the Address and Control fields.
All SDLC information is sent in frames and follow a standard format as shown in Figure
4–4. SDLC frames begin and end with the 8-bit flag sequence, “01111110.” All stations
on the link search continuously for this flag sequence which indicates the start of a frame
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PDF描述 |
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| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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