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| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 140/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Register Description
AMD
6–30
Bit 7: Break/Abort IE
If this bit is set to ‘1’, a change in the Break/Abort status of the receiver causes an Exter-
nal/Status interrupt. This bit is set by a channel or hardware reset.
Bit 6: Tx Underrun/EOM
If this bit is set to ‘1’, a change of state by the Tx Underrun/EOM latch in the transmitter
causes an External/Status interrupt. This bit is set to ‘1’ by a channel or hardware reset.
Bit 5: CTS IE
If this bit is set ‘1’, a change of state on the
CTS
pin causes an External/Status interrupt.
This bit is set by a channel or hardware reset.
Bit 4: SYNC/Hunt IE
If this bit is set to ‘1’, a change of state on the
SYNC
pin causes an External/Status inter-
rupt in Asynchronous mode, and a change of state in the Hunt bit in the receiver causes
an External/Status interrupt in synchronous modes. This bit is set by a channel or hard-
ware reset.
Bit 3: DCD IE
If this bit is set to ‘1’, a change of state on the
DCD
pin causes an External/Status inter-
rupt. This bit is set by a channel or hardware reset.
Bit 2 10x19–Bit Frame Status FIFO Enable
If this bit is set to ‘1’, the 10X19-bit FIFO array and 14-bit counter are available for use but
only if the SCC is programmed in SDLC mode.
Bit 1: Zero Count IE
If this bit is set to ‘1’, an External/Status interrupt is generated whenever the counter in
the baud rate generator reaches ‘0’. This bit is set to ‘0’ by a channel or hardware reset.
Bit 0: SDLC/HDLC Enhancement Enable
If this bit is set to ‘1’, WR7
′
can be accessed as WR7
′
to allow the use of special SDLC/
HDLC options. Refer to WR7
′
for details.
6.3
The SCC contains nine read registers in each channel. The status of these registers is
continually changing and depends on the mode of communication, received and transmit-
ted data, and the manner in which this data is transferred to and from the CPU. The fol-
lowing description details the bit assignments for each register.
READ REGIS T ERS
6.3.1
Read Register 0 (T ransmit/Rec eive Buffer S tatus
and External S tatus)
Read Register 0 contains the status of the receive and transmit buffers. RR0 also con-
tains the status bits for the six sources of External/Status interrupts. The bit configuration
is illustrated in Figure 6–18.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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