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參數(shù)資料
| 型號： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 69/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Data Communication Modes Functional Description
AMD
4–17
Since not all status bits of RR1 are stored in the Frame Status FIFO, the All Sent, Parity,
and EOF bits bypass the FIFO and are stored in the 8-bit Status FIFO. The status bits
stored in the 10x19-bit FIFO will be the Residue, Overrun, and CRC status bits. Note that
the EOF interrupt is generated the same way as before.
4.7.1.3.3
When an EOF is detected, and the FIFO is enabled, the five status bits and byte-count
are loaded into the FIFO, and the FIFO pointer is incremented. If the FIFO overflows, bit
D7 of RR7 (FIFO Overflow) is set to indicate the overflow. This bit and the FIFO control
logic is reset by disabling and re-enabling the FIFO control bit (WR15 bit D2). For details
of FIFO control timing during an SDLC frame, refer to Figure 4–14.
FIFO Write Operation
When a packet is completely received, then a Receive Interrupt on Special Condition is
generated upon receipt of the End of Frame Flag. If the clock is temporarily stopped after
the receipt of the flag, the Frame Status FIFO may not be updated even though the inter-
rupt was generated. At least two receive clocks are needed to update the Frame Status
FIFO. The Frame Status information is not lost and will be put into the Frame Status FIFO
when the clock is enabled again.
4.7.1.3.4
The 14-bit byte counter allows for data frames of up to 16K bytes to be received. It is en-
abled when bit D2 of WR15 is set to ‘1’ and the SCC is in SDLC mode. It is reset when-
ever an SDLC flag character is received. The reset is timed so that the contents of the
byte counter are successfully written into the FIFO.
14-Bit Byte Counter
The byte counter is incremented by writes to the 8-bit receive Data FIFO. The counter
represents the number of bytes received by the SCC, rather than the number of bytes
transferred from the SCC. (These counts may differ by up to the number of bytes in the
receive data FIFO contained in the SCC.)
FOY
FDA
BC
13
6
5
7
FIFO Data Available Status
1 = Status Reads Will Come From FIFO
0 = Status Reads Will Come From SCC
FIFO Overflow Status
1 = FIFO Overflowed During Operation
0 = Normal
RR7
0
BC
0
Read From FIFO
LSB Byte Count
RR6
4
BC
12
3
BC
11
2
BC
10
1
BC
9
0
BC
8
7
BC
7
6
BC
6
5
BC
5
4
BC
4
3
BC
3
2
BC
2
1
BC
1
0
*
Status FIFO Enable Control Bit
1 =
Status and Byte Count Will be
Held in the Status FIFO Until Read
WR16
7
*
6
*
5
*
4
*
3
*
2
FEN
1
*
0 = Status Will Not be Held (SCC)t
(Emulation Mode)
* = No Change From NMOS SCC DFN
10216A-013A
Figure 4–13. Frame Status FIFO Registers
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PDF描述 |
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| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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