
SCC Application Notes
AMD
7–12
Table 7–6. SCC Initialization Order for Interrupt Driven Asynchronous Mode
Register
WR9
WR4
WR2
WR3
WR5
WR9
WR10
WR11
WR12
WR13
WR14
Enables
WR14
WR3
WR5
Enable Interrupts
WR1
WR9
Value
C0H
4CH
00H
C0H
60H
00H
00H
56H
06H
00H
10H
Comments
Force Hardware Reset
x 16 clock, 2 stop bits, no parity
Interrupt Vector 00
Rx 8 bits, Rx disabled
Tx 8 bits, DTR, RTS, Tx off
Int Disabled
NRZ
Tx & Rx = BRG out, TRxC = BRG out
Time constant = 6
Time constant high = 0
BRG in = RTxC, BRG of, loopback
11H
C1H
68H
BRG enable
Rx enable
Tx enable
12H
08H
Rx Int on all char and Tx Int enables
MIE
7.3.3.1
WR9
resets SCC to a known state by writing a C0 hex. This command, Force Hardware
Reset, is identical to a hardware reset. It will reset both channels.
S CC Operating Modes Programming
WR4
selects asynchronous mode, x16 mode, 2 stop bits and no parity. The x16 mode
means that the clock rate is 16 times the data rate.
WR2
is the interrupt vector of the SCC. Even though a vector is not placed in the bus in
this mode the vector including status is read from RR2. By writing 00H to this register the
status read will be the only bits set in RR2.
WR3
selects 8 bits per character and does not enable the receiver. The 8 bits per charac-
ter allows 8 bits to be assembled from the data stream. The receiver is not enabled at this
time because the SCC is not completely initialized.
WR5
selects 8 bits per character and does not enable the transmitter. The 8 bits per char-
acter allows 8 bits to be sent as data with the least significant bit first. The transmitter is
not enabled at this time because the SCC is not completely initialized.
WR9
selects that there are no interrupts enabled. This will inhibit the SCC from request-
ing an interrupt from the CPU.
WR10
selects NRZ encoding. This selects NRZ coding that is to be used on the transmit-
ter and the receiver.
WR11
selects the
RTxC
pin to TTL clock, the transmit and receive clocks source as the
baud-rate generator and the
TRxC
pin as a baud-rate generator output.