- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366552 > AM8530H (Advanced Micro Devices, Inc.) Serial Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 139/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)當(dāng)前第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)
Register Description
AMD
6–29
RxD input. Transmitted data are never seen inside or outside the SCC in this mode, and
CTS
is ignored as a transmit enable. This bit is reset by a channel or hardware reset.
Bit 2: DTR/Transmit DMA Request Function
This bit selects the function of the
DTR
/
REQ
pin. If this bit is set to ‘0’, the
DTR
/
REQ
pin
follows the inverted state of the DTR bit in WR5. If this bit is set to ‘1’, the
DTR
/
REQ
pin
goes Low whenever the transmit buffer becomes empty and in any of the synchronous
modes when CRC has been sent at the end of a message. The request function on the
DTR
/
REQ
pin differs from the transmit request function available on the
W
/
REQ
pin in
that Request does not go inactive until the internal operation satisfying the request is
complete, which occurs four to five PCLK cycles after the rising edge of READ or WRITE.
If the DMA used is edge-triggered, this difference is unimportant. This bit is reset by a
channel or hardware reset.
Bit 1: Baud Rate Generator Source
This bit selects the source of the clock for the baud rate generator. If this bit is set to ‘0’,
the baud rate generator clock comes from either the
RTxC
pin or the XTAL oscillator (de-
pending on the state of the XTAL/no XTAL bit). If this bit is set to ‘1’, the clock for the
baud rate generator is the SCC’s PCLK input. Hardware reset sets this bit to ‘0’, select-
ing the
RTxC
pin as the clock source for the baud rate generator.
Bit 0: Baud Rate Generator Enable
This bit controls the operation of the baud rate generator. The counter in the baud rate
generator is enabled for counting when this bit is set to ‘1’, and counting is inhibited when
this bit is set to ‘0’. When this bit is set to ‘1’, change in the state of this bit is not reflected
by the output of the baud rate generator for two counts of the counter. This allows the
command to be synchronized. However, when set to ‘0’, disabling is immediate. This bit is
reset by a hardware reset.
6.2.16
Write Register 15 (External/S tatus Interrupt
Control)
WR15 is the External/Status source control register. If the External/Status interrupts are
enabled as a group via WR1, bits in this register control which External/Status conditions
can cause an interrupt. Only the External/Status conditions that occur after the controlling
bit is sent to ‘1’, will cause an interrupt. This is true even if an External/Status condition is
pending at the time the bit is set. Bit positions for WR15 are shown in Figure 6–17.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DCD IE
SYNC/HUNT IE
CTS IE
Tx Underrun/EOM IE
SDLC/HDLC Enhancement Enable
Zero Count IE
10 x 19-Bit Frame Status FIFO Enable
Break/Abort IE
Figure 6–17. Write Register 15
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。