
SCC Application Notes
7–42
array[23]=0xFD;
array[24]=0x5;
array[25]=0x6B;
array[26]=0x00;
array[27]=0x80;
array[28]=0x1;
array[29]=0xE0;
array[30]=0xF;
array[31]=0x00;
array[32]=0x0;
array[33]=0x10;
array[34]=0x0;
array[35]=0x10;
array[36]=0x1;
array[37]=0xE0;
array[38]=0x9;
array[39]=0x02;
/*Rx enable*/
/*Tx enable*/
/*reset TxCRC*/
/*DMA request enabled*/
/*disable all interrupts*/
/*reset external/status interrupt twice*/
/*Rx interrupt on special condition*/
/*set master interrupt enable to 1*/
/*BEGIN INITIALIZATION ROUTINE*/
/*The following dummy read statement is used to ensure that SCC
has initialized properly*/
temp = inportb(port);
/*read from RR0*/
while(i<arraysize)
{
outportb(port, array[i++]);
}
}
/*THIS ROUTINE INITIALIZES THE 9517 DMA CONTROLLER*/
dmainit()
{
unsigned int lsb, temp, msb, latch, wrdh, wrd1, tmp1, start;
unsigned int bytn, byt, tmp2;
outportb(0x09, 0x01); /*clear all DMA requests on channel 1*/
outportb(0x0A, 0x05); /*mask channel 1 DMA request*/
outportb(0x0B, 0x45); /*mode register for single transfer mode,
read, auto init, address increment*/
lsb = adrr & 0xFF;
temp = adrr >> 0x08;
/*rotate ptr 8 bits to get msb*/
msb = tem[ & 0xFF;
temp = temp >> 0x08;
/*rotate 8 bits to get sector address*/
latch = temp & 0x0F;
outportb(0x81, latch);/*load sector address into DMA page reg-
ister*/
outportb(0x02, lsb);
/*lower byte of starting address*/
outportb(0x02, msb);
/*upper byte of starting address*/
start = adrr & 0xFFFF;
bytn = 0x03;
wrd1 = bytn & 0xFF;
/*lower order byte of wordcount*/
tmp1 = bytn >> 0x08;
/*rotate wordcount 8 bits for msb*/
wrdh = tmp1 & 0xFF;
/*upper byte of wordcount*/
outportb(0x03, wrd1); /*this is the lower byte of # of bytes
that fit within the first sector
outportb(0x03, wrdh); /*upper byte of wordcount*/
outportb(0x0A, 0x01); /*enable DMA*/
}
/*THIS ROUTINE WRITES THE MEMORY BUFFER ON TO THE DISK*/
closfile()
{
char var_nam, name[10];