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參數(shù)資料
| 型號： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 144/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Register Description
AMD
6–34
have been read out by a DMA controller independently from the CPU but the CRC status
is still available in the Frame Status FIFO.
Bit 5: Receiver Overrun Error
This bit indicates that the receive FIFO has overflowed. Only the character that has been
written over is flagged with this error, and when the character is read, the Error condition
is latched until reset by the Error Reset command. The overrun character and all subse-
quent characters received until the Error Reset command is issued causes a Special Re-
ceive Condition vector to be returned.
Bit 4: Parity Error
When parity is enabled, this bit is set for the characters whose parity does not match the
programmed sense (even/odd). This bit is latched so that once an error occurs, it remains
set until the Error Reset command is issued. If the parity in Special Condition bit is set, a
parity error causes a Special Receive Condition vector to be returned on the character
containing the error and on all subsequent characters until the Error Reset command is
issued.
Bits 3, 2, and 1: Residue Codes 2, 1, And 0
In those cases in SDLC mode where the received I-Field is not an integral multiple of the
character length, these three bits indicate the length of the I-Field and are meaningful
only for the transfer in which the end of frame bit is set. This field is set to “011” by a
channel or hardware reset and is forced to this state in Asynchronous mode. These three
bits can leave this state only if SDLC is selected and a character is received. The codes
signify the following (reference Table 6–9) when a receive character length is eight bits
per character.
I-Field bits are right–justified in all cases. If a receive character length other than eight bits
is used for the I-Field, a table similar to Table 6–9 can be constructed for each different
character length. Table 6–10 shows the residue codes for no residue (the I-Field bound-
ary lies on a character boundary).
Table 6–9. I-Field Bit Selection (8 Bits Only)
I-Field
Bits in
Last Byte
0
0
0
0
0
0
1
2
I-Field
Bits in
Previous Byte
3
4
5
6
7
8
8
8
Residue
0
1
0
1
0
1
0
1
0
Residue
1
0
1
1
0
0
1
1
0
Residue
2
0
0
0
1
1
1
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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