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參數(shù)資料
| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 73/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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SLAC Products
75
GR filter
EGR = 0*
GR filter default coefficients used:
EGR = 1
GR filter programmed coefficients used
GX filter
EGX = 0*
GX filter default coefficients used
EGX = 1
GX filter programmed coefficients used
X filter
EX = 0*
X filter default coefficients used
EX = 1
X filter programmed coefficients used
R filter
ER = 0*
R filter default coefficients used
ER = 1
R filter programmed coefficients used
Z filter
EZ = 0*
Z filter default coefficients used
EZ = 1
Z filter programmed coefficients used
B filter
EB = 0*
B filter default coefficients used
EB = 1
B filter programmed coefficients used
*Power Up and Hardware Reset (RST) Value = 00h
SOP 8.Write/Read SLIC I/O Direction and Status Bits
GCI Command
(54/55h)
SLIC I/O Direction and Status Bits (Configuration Register 4, CR4)
Pins CD1, CD2 and C3 through C5 are set to Input or Output modes individually. Pin C5 is not
available on the Am79Q06 and Pins C3–C5 are not available on the Am79Q062 QSLAC devices.
RSVD:
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read only, write as 0)
CSTAT = 0
Channel is inactive (Standby mode)
CSTAT = 1
Channel is active
Clock Fail (Read only, write as 0)
CFAIL = 0
The internal clock is synchronized to frame sync
CFAIL = 1
The internal clock is not synchronized to frame sync
The CFAIL bit is universal for the QSLAC device and is independent of the channel addressed.
IOD1–IOD5
Programmable I/O direction control (CD1, CD2, C3, C4, C5 pins)
*0 = Pin is set as an input port
1 = Pin is set as an output port
*Power Up and Hardware Reset (RST) Value = 00h
Bit
7
6
5
4
3
2
1
0
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
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