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參數(shù)資料
| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 39/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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44
Am79Q06/061/062/063 Data Sheet
SLIC status
XDAT
-
Transmit PCM data
Commands are provided to assign values to the
following global chip parameters:
XE
-
Transmit PCM Clock Edge
RCS
-
Receive Clock Slot
TCS
-
Transmit Clock Slot
INTM
-
Interrupt Output Drive Mode
CHP
-
Chopper Clock Frequency
ECH
-
Enable Chopper Clock Output
SMODE
-
Select Signaling on the PCM
Highway
CMODE
-
Select Master Clock Mode
CSEL
-
Select Master Clock Frequency
EC
-
Channel Enable Register
DSH
-
Debounce Time for CD1
EE1
-
Enable E1 Output
E1P
-
E1 Polarity
MCDxy
-
Interrupt Mask Register
Commands are provided to read values from the
following global chip status monitors:
CDxy
-
Real Time Data Register
PI
-
Power Interruption Bit
CFAIL
-
Clock Failure Bit
RCN
-
Revision Code Number
The following description of the MPI (Microprocessor
Interface) is valid for Channel 1, 2, 3, or 4. If desired,
multiple channels can be programmed simultaneously
with identical information by setting multiple Channel
Enable bits. Channel enables are contained in the
Channel Enable Register and are written or read using
Commands 14 and 15. If multiple Channel Enable bits
are set for a read operation, only data from the first
enabled channel is read.
The MPI physically consists of a serial data input/output
(DIO), a data clock (DCLK), and a chip select (CS).
Individual Channel Enable bits EC1, EC2, EC3, and
EC4 are stored internally in the Channel Enable
Register of the QSLAC device. The serial input consists
of 8-bit commands that can be followed with additional
bytes of input data, or can be followed by the QSLAC
device sending out bytes of data. All data input and
output is MSB (D7) first and LSB (D0) last. All data bytes
are read or written one at a time, with CS going High for
at least a minimum off period before the next byte is
read or written. Only a single channel should be enabled
during read commands.
All commands that require additional input data to the
device must have the input data as the next N words
written into the device (for example, framed by the next
N transitions of CS). All unused bits should be
programmed as 0 to ensure compatibility with future
parts. All commands that are followed by output data will
cause the device to output data for the next N transitions
of CS going Low. The QSLAC device will not accept any
commands until all the data has been shifted out. The
output values of unused bits are not specified.
An MPI cycle is defined by transitions of CS and DCLK.
If the CS lines are held in the High state between
accesses, the DCLK runs continuously with no change
to the internal control data. Using this method, the same
DCLK can be run to a number of QSLAC devices and
the individual CS lines will select the appropriate device
to access. Between command sequences, DCLK can
stay in the High state indefinitely with no loss of internal
control information regardless of any transitions on the
CS lines. Between bytes of a multibyte read or write
command sequence, DCLK can also stay in the High
state indefinitely. DCLK can stay in the Low state
indefinitely with no loss of internal control information,
provided the CS lines remain at a High level.
If a low period of CS contains less than 8 positive DCLK
transitions, it is ignored. If it contains 8 to 15 positive
transitions, only the last 8 transitions matter. If it contains
16 or more positive transitions, a hardware reset in the
part occurs. If the chip is in the middle of a read
sequence when CS goes Low, data will be present at the
DIO pin even if DCLK has no activity. If CS is held low
for two or more cycles of Frame Sync (FS) and DCLK is
static (no toggling), then the QSLAC device switches to
the General Circuit Interface mode of operation.
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