參數(shù)資料
型號(hào)： AM79Q062JC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 編解碼器
英文描述： A/MU-LAW, PCM CODEC, PQCC32
封裝： PLASTIC, LCC-32
文件頁數(shù)： 31/95頁
文件大小： 1399K
代理商： AM79Q062JC
SLAC Products
37
Figure 11. MPI Real-Time Data Register or GCI Upstream SC Channel Data
Real-Time Data Register Operation
To obtain time-critical data such as off/on-hook and
ring trip information from the SLIC with a minimum of
processor time and effort, the QSLAC device contains
an 8-bit Real Time Data register. This register contains
CDA and CDB bits from all four channels. The CDA bit
for each channel is a debounced version of the CD1
input. The CDA bit is normally used for switchhook.
The CDB bit for each channel normally contains the
CD2 input bit; however, if the E1 multiplex operation is
enabled, the CDB bit will contain the debounced value
of the CD1B bit. CD1 and CD2 can be assigned to off-
hook, ring trip, ground key signals, or other signals.
Frame sync is needed for the debounce and the
ground-key signals. If Frame sync is not provided, the
real-time register will not work. The register is read
using MPI Commands 16 and 17 or GCI Command
SOP 13 (4D/4Fh), and may be read at any time
regardless of the state of the Channel Enable
Register. This allows off/on-hook, ring trip, or ground
key information for all four channels to be obtained
from the QSLAC device with one read operation
versus one read per channel. If these data bits are not
used for super vision info r m ation, they can be
accessed on an individual channel basis in the same
way as C3–C5; however, CD1 and CD1B will not be
debounced. This Real-Time Data register is available
in both MPI and GCI modes. In the GCI mode, this
real-time data is also available in the field of the
upstream SC octet.
Interrupt
In addition to the Real Time Data register, an interrupt
signal is provided by the QSLAC device. The Interrupt
signal is an active Low output signal that pulls Low any
time any of the unmasked CD bits changes state (Low
1 kHz
UP/DN
GK=0
Six-State
Up/Down
GK
GK=0
Counter
*
a. Loop Detect Debounce Filter
8
DQ
RST
D
Q
EN/HOLD
FS
(8 kHz)
CD1
CDA
CK
DSH0–DSH3
Debounce Period
(0–15 ms)
Q
Debounce Counter
* Transparent latch: Output follows input when EN is high; output holds last state when EN is low
Debounce Counter: Output goes high after counting to programmed (DSH) number of 1 ms clocks;
Counter is reset for CD1 input changes at 125
s sample period.
DSH0–DSH3 programmed value is common for all 4 channels, but debounce counter is separate per channel
Notes:
RST
GK0–GK3
Ground-Key
(1–15 ms)
Sampling Interval
Q
CD2 or CD1B
CDB
MUX
Clock Divider
(1–15 ms
clock output)
b. Ground-Key Filter
Programmed value of GK0–GK3 determines clock rate (1–15 ms) of six-state counter.
Notes:
If GK value = 0, counter is bypassed and no buffering occurs.
Six-state up/down counter: Counts up when input is high; counts down when input is low.
Output goes and stays high when maximum count is reached;
output goes and stays low when counts down to zero.
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