- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄166217 > AM79Q062JC (ADVANCED MICRO DEVICES INC) A/MU-LAW, PCM CODEC, PQCC32 PDF資料下載
參數(shù)資料
| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 33/95頁 |
| 文件大小： | 1399K |
| 代理商： | AM79Q062JC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁
SLAC Products
39
SIGNAL PROCESSING
Overview of Digital Filters
Several of the blocks in the signal processing section are user-programmable. These allow the user to optimize the
performance of the QSLAC device for the system. Figure 12 shows the QSLAC device signal processing and indicates
the programmable blocks.
The advantages of digital filters are
s High reliability
s No drift with time or temperature
s Unit-to-unit repeatability
s Superior transmission performance
s Flexibility
s Maximum possible bandwidth for V.34 modems.
Two-Wire Impedance Matching
Two feedback paths on the QSLAC device synthesize
the two-wire input impedance of the SLIC by providing
a programmable feedback path from VIN to VOUT. The
Analog Impedance Scaling Network (AISN) is a
programmable analog gain of –0.9375 to +0.9375 from
VIN to VOUT. The Z filter is a programmable digital filter
providing an additional path and programming flexibility
over the AISN in modifying the transfer function from
VIN to VOUT. Together, the AISN and the Z-filter enable
the user to synthesize virtually all required SLIC input
impedances.
Frequency Response Correction
and Equalization
The QSLAC device contains programmable filters in the
receive (R) and transmit (X) directions that can be
programmed for line equalization and to correct any
attenuation distortion caused by the Z filter.
Transhybrid Balancing
The QSLAC device’s programmable B filter is used to
adjust transhybrid balance. The filter has a single pole
IIR section (BIIR) and an eight-tap FIR section (BFIR),
both operating at 16 kHz.
Gain Adjustment
T he Q S LAC de v i c e ’s tr ans mit pa th has tw o
programmable gain blocks. Gain block AX is an analog
gain of 0 dB or 6.02 dB (unity gain or gain of 2.0),
located immediately before the A/D converter. GX is a
digital gain block that is programmable from 0 dB to +12
dB, with a worst-case step size of 0.1 dB for gain
settings below +10 dB, and a worst-case step size of
0.3 dB for gain settings above +10 dB. The filters
provide a net gain in the range of 0 dB to 18 dB.
The QSLAC device receive path has two programmable
loss block s. GR is a digital los s block that i s
programmable from 0 dB to 12 dB, with a worst-case
step size of 0.1 dB (unity gain or gain of 0.5). Loss block
AR is an analog loss of 0 dB or 6.02 dB, located
immediately after the D/A converter. This provides a net
loss in the range of 0 dB to 18 dB.
An additional 6 dB attenuation is provided as part of
GR, which can be inserted by setting the RG bit of
Command 70/71h. This allows writing of a single bit to
introduce 6 dB of attenuation into the receive path with-
out having to reprogram GR. This 6 dB loss is imple-
TSA
AR
AISN
Cutoff
Transmit
Path
(CTP)
Lower Receive
Gain (LRG)
Full
Digital
Loop
back
(FDL)
GX
AX
TSA
Loopback
(TLB)
R
GR
X
ADC
Deci-
mator
DAC
LPF
& HPF
Com-
pressor
Ex-
pander
LPF
VOUT
VIN
TSA
B
Inter-
polator
Figure 12. QSLAC Device Block Diagram
+
Z
Digital
TX
Digital
RX
Inter-
polator
Deci-
mator
21108-027
High Pass Filter (HPF)
0
1 kHz Tone
(TON)
Cutoff Receive
Path (CRP)
VREF
*
* programmable blocks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM80A-048L-050P25 | 1-OUTPUT 125 W DC-DC REG PWR SUPPLY MODULE |
| AM8152BDC | SPECIALTY INTERFACE CIRCUIT, CDIP48 |
| AMB315218 | MOTION SENSOR, XSS |
| AMCY-ED12566/1 | 880 MHz - 915 MHz RF/MICROWAVE DOUBLE BALANCED MIXER |
| AMDL-250G | ACTIVE DELAY LINE, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79Q063VC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q2241VC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q2242JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q2243VC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q4457 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。