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參數(shù)資料
| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 27/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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SLAC Products
33
SLIC Control and Data Lines
The QSLAC device has up to five programmable Input/
Output pins per channel (CD1–C5). Each of these pins
can be programmed as either an input or an output
using the I/O Direction Register (MPI Commands 22
and 23, G C I Command S O P 8) . Al so, the
Am79Q063VC 64-pin package includes two additional
output pins per channel, C6-C7 (see Figure 9). The
output latches can be written with MPI Command 20 or
through the CI1 to CI5 bits present in the downstream
SC channel; however, only those bits programmed as
outputs actually drive the pins. The inputs can be read
with MPI Command 21, GCI Command SOP 10 or on
the Upstream CI bits, in the SC channel. If a pin is
programmed as an output, the data read from it is the
contents of the output latch. In the GCI mode, this data
can be read using SOP 10, but the output bits are not
sent upstream in the SC channel.
Clock Mode Operation
The QSLAC device operates with multiple clock signals.
The master clock (MCLK) is used for internal timing
including operation of the digital signal processing. In
PCM/MPI mode, the master clock may be derived from
either the MCLK or PCLK source. In GCI mode, the
master clock is obtained from the DCL clock only. The
allowed frequencies are listed under Commands 12 and
13 for PCM/MPI mode. In GCI mode, DCL can be only
2.048 MHz or 4.096 MHz.
In PCM/MPI mode, the PCM clock (PCLK) is used for
PCM timing and is an integer multiple of the frame sync
frequency. The internal device clock (MCLK) can be
optionally derived from the PCLK source by setting the
CMODE bit (bit 4, commands 12 and 13, 46/47h) to one.
In this mode, the MCLK/E1 pin is free to be used as an
E1 signal output. In GCI mode, since the master clock is
derived only from the DCL clock, this MCLK/E1 pin is
always available as an E1 output. Clock mode options
and E1 output functions are shown in Figure 8.
.
Figure 8. Clock Mode Option (PCM/MPI Mode)
Time
Slot
Assigner
DSP
Engine
E1
Pulses
E1P
PCLK
MCLK/E1
N
÷
CSEL
CMODE
(= 1)
(= 0)
E1
(= 1)
(= 0)
EE1
Notes:
1. CMODE = Command 12, 13
Bit 4
2. CSEL = Command 12, 13
Bits 0–3
3. EE1 = Command 45, 46
Bit 7
4. E1P = Command 45, 46
Bit 6
(= 0)
(= 1)
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| AM79Q063VC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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| AM79Q2242JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q2243VC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q4457 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices |
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