參數(shù)資料
型號(hào)： AM79Q062JC
廠(chǎng)商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 編解碼器
英文描述： A/MU-LAW, PCM CODEC, PQCC32
封裝： PLASTIC, LCC-32
文件頁(yè)數(shù)： 26/95頁(yè)
文件大小： 1399K
代理商： AM79Q062JC
32
Am79Q06/061/062/063 Data Sheet
OPERATING THE QSLAC DEVICE
The following sections describe the operation of the four
independent channels of the QSLAC device. The
desc r iption is valid for Channel 1, 2, 3, or 4;
consequently, the channel subscripts have been
dropped. For example, VOUT refers to either VOUT1,
VOUT2, VOUT3, or VOUT4.
Power-Up Sequence
The recommended QSLAC device power-up sequence
is to apply:
1.
Ground first
2.
VCC, signal connections, and Low on RST
3.
High on RST
The software initialization should then include:
1.
Wait 1 ms.
2.
For PCM/MPI mode, select master clock frequency
and source (Commands 12 and 13). This should
turn off the CFAIL bit (Command 23) within 400
s.
While the CFAIL bit is on, normal programming can
proceed, but no channels should be activated.
In GCI mode, DCL is the clock source. The CFAIL
bit (GCI Command SOP 8) is set to 1 until the
device has determined and synchronized to the
DCL frequency, 4.096 MHz or 2.048 MHz. While
the CFAIL bit is on, normal programming can
proceed, but no channels should be activated. If
channels are activated while CFAIL is a 1, no
device damage will occur, but high audible noise
may appear on the line. Also, CD1, CD2, C3, C4,
and C5 bit may not be stable.
3.
Program filter coefficients and other parameters
as required.
4.
Activate (MPI Command 5, GCI Command SOP 04).
If the power supply (VCCD) falls below approximately
1.0 V, the device is reset and requires complete
reprogramming with the above sequence. A reset can
be initiated by connection of a logic Low to the RST pin,
or if chip select (CS) is held low for 16 rising edges of
DCLK, a hardware reset is generated when
CS returns
high. The RST pin can be tied to VCCD if it is not used
in the system.
PCM and GCI State Selection
The Am79Q06/061/062/063 QSLAC device can switch
between PCM/MPI and GCI states. Table 2 lists the
selection requirements.
Table 2. PCM/GCI State Selection
Channel Enable Register
In PCM/MPI mode, a channel enable register has been
implemented in the QSLAC device in order to reduce
the effort required to address individual or multiple
channels of the QSLAC device. The register is written
using MPI Command 14. Each bit of the register is
assigned to one unique channel, bit 0 for Channel 1, bit
1 for Channel 2, bit 2 for Channel 3, and bit 3 for
Channel 4. The channel or channels are enabled when
their corresponding enable bits are High. All enabled
channels receive the data written to the QSLAC device.
This enables a Broadcast mode (all channels enabled)
to be implemented simply and efficiently, and multiple
channel addressing is accomplished without increasing
the number of I/O pins on the device. The Broadcast
mode can be further enhanced by providing the ability to
select many chips at once; however, care should be
taken not to enable more than one chip in the Read
mode. This can lead to an internal bus contention,
where excess power is dissipated. (Bus contention will
not damage the device.) Most MPI commands defined
for the DSLAC device are compatible with the QSLAC
device, thereby minimizing the impact to existing
system software.
In GCI mode, the individual channels are controlled by
their respective Monitor and SC channels embedded in
the GCI channels selected by the device (S0, S1).
From State
To State
Requirement
Power On or
Hardware
Reset
PCM
CS = 1 or DCLK has ac
clock present
Power On or
Hardware
Reset
GCI
CS = 0 and DCLK does
not have ac clock
present
GCI
PCM
CS = 1 or DCLK has ac
clock present
PCM
GCI
No commands yet sent
in PCM state and CS =0
(for more than 2 FS) and
DCLK does not have ac
clock present
PCM
Power On or
Hardware
Reset
Commands have been
sent in PCM state and
Hardware Reset
generated
GCI
Power On or
Hardware
Reset
Not allowed
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