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參數(shù)資料
| 型號(hào)： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 28/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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34
Am79Q06/061/062/063 Data Sheet
E1 Multiplex Operation
The QSLAC device can multiplex input data from the
CD1 SLIC I/O pin into two separate status bits per
channel (CD1 and CD1B bits in the SLIC Input/Output
register, Commands 52/53h, and CDA and CDB bits in
the Real Time Data register, Commands 4D/4Fh)
using the E1 multiplex mode. This multiplex mode
provides the means to accommodate dual detect
states when connected to an AMD SLIC device, which
also supports ground-key detection in addition to loop
detect. AMD SLICs that support ground-key detect
use their E1 pin as an input to switch the SLIC’s single
detector (DET) output between internal loop detect or
grou nd-key de tect comp arators. Using the E1
multiplex mode, a single QSLAC device can monitor
both loop detect and ground-key detect states of all
four connected SLICs without additional hardware.
Although normally used for ground key detect, this
multiplex function can also be used for monitoring
other signal states.
The E1 multiplex mode is selected by setting the EE1
bit (bit 7, Command C8/C9h) and CMODE bit (bit 4,
Command 46/47h) in the QSLAC device. The CMODE
bit must be selected (CMODE = 1) for the master clock
to be derived from PCLK so that the MCLK/E1 pin can
be used as an output for the E1 signal. The multiplex
mode is then turned on by setting the EE1 bit. With the
E1 multiplex mode enabled, the QSLAC device
generates the E1 output signal. This signal is a
31.25
s (1/32 kHz) duration pulse occurring at a
4.923 kHz (64 kHz/13) rate. The polarity of this E1
output is selected by the E1P bit (bit 6, Command C8/
C9h) allowing this multiplex mode to accommodate all
SLICs regardless of their E1 high/low logic definition.
Figure 9 shows the SLIC Input/Output register, I/O
pins, E1 multiplex hardware operation for one QSLAC
device channel. It also shows the operation of the Real
Time Register. The QSLAC device E1 output signal
connects directly to the E1 inputs of all four connected
SLICs and is used by those SLICs to select an internal
comparator to route to the SLIC’s DET output. This E1
signal is also used internally by the QSLAC device for
controlling the multiplex operation and timing.
The CD1 and CD1B bits of the SLIC Input/Output
register are isolated from the CD1 pin by transparent
latches. When the E1 pulse is off, the CD1 pin data is
routed directly to the CD1 bit of the SLIC I/O register
and changes to the CD1B bit of that register are
disabled by its own latch. When E1 pulses on, the CD1
latch holds the last CD1 state in its register. At the
same time, the CD1B latch is enabled, which allows
CD1 pin data to be routed directly to the CD1B bit.
Therefore, during this multiplexing, the CD1 bit always
has loop-detect status and the CD1B bit always has
ground-key detect status.
T h is
multiple xi ng
state
changes
almost
instantaneously within the QSLAC device but the SLIC
device may require a slightly longer time period to
respond to this detect state change before its DET
output settles and becomes valid. To accommodate
this delay difference, the internal signals within the
QSLAC device are isolated by 15.625
s before
allowing any change to the CD1 bit and CD1B bit
latches. This operation is further described by the E1
multiplex timing diagram in Figure 10. In this timing
diagram, the E1 signal represents the actual signal
presented to the E1 output pin. The GK Enable pulse
allows CD1 pin data to be routed through the CD1B
latch. The LD Enable pulse allows CD1 pin data to be
routed through the CD1 latch. The uncertain states of
the SLIC’s DET output, and the masked times where
that DET data is ignored are shown in this timing
diagram. Using this isolation of masked times, the
CD1 and CD1B registers are guaranteed to contain
accurate representations of the SLIC detector output.
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