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參數(shù)資料
| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 61/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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64
Am79Q06/061/062/063 Data Sheet
GCI Format and Command Structure
The GCI interface provides communication of both
control and voice data between the GCI highway and
subscriber line circuits over a single pair of pins on the
QSLAC device. A complete GCI frame is sent upstream
on the DU pin and received downstream on the DD pin
every 125 s. Each frame consists of eight 4 byte GCI
channels (CHN0 to 7) that contain voice and control
information for eight pairs of channels. A particular
channel pair is identified by its position within the frame
(see Figure 15). Therefore, a total of 16 voice channels
can be uniquely addressed each frame. The overall
structure of the GCI frame is shown in Figure 15.
The 4 byte GCI channel contains the following:
s 2 bytes; B1 and B2 for voice channels 1 and 2.
s One Monitor (M) byte for reading/writing control
data/coefficients to the QSLAC for both channels.
s One Signaling and Control (SC) byte containing a
6-bit Command/Indicate (C/I) channel for control
information and a 2-bit field with Monitor Receive
and Monitor Transmit (MR, MX) bits for handshaking
functions for both channels. All principal signaling
(real-time critical) information is carried on the C/I
channel. The QSLAC device utilizes the full C/I
channel capacity of the GCI channel.
SC Channel
The upstream and downstream SC channels are continuously carrying I/O information every frame to and from the
QSLAC device in the C/I field. This allows the upstream processor to have immediate access to the output
(downstream) and input (upstream) data present on the QSLAC device’s programmable I/O port.
The MR and MX bits are used for handshaking during data exchanges on the monitor channel.
Downstream C/I Channel
The QSLAC device receives the MSBs first.
The downstream C/I channel SC octet definition depends on the device package type. The 44-pin and 32-pin packages
do not have provisions for pin connections to accommodate all SLIC outputs, which otherwise are available on the
higher pin count devices. For the 32-pin and 44-pin package devices, the downstream SC octet is defined as:
<---------------- Downstream SC Octet ------------------>
|<------------------- C/I Field ------------------->|
MSB
LSB
7
6
5
4
3
2
1
0
A
C5x
C4x
C3x
CD2x
CD1x
MR
MX
DU, DD
CHN0
CHN1
CHN2
CHN3
CHN4
CHN5
CHN6
CHN7
0
3
4
7
8
11
12
15
16
19
20
23
24
27
28
31
FS
B1
B2
M
SC
MR
MX
C/I
8
1
0
8
2
8
3
6
1
Figure 15. Multiplexed GCI Time Slot Structure
21108A-029
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