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參數(shù)資料
| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 3/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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SLAC Products
11
DXA,
DXB/DU
Outputs
PCM Data Transmit. In the PCM/MPI mode, the transmit data from Channels 1, 2, 3, and 4 is sent
serially out on either the DXA or DXB port or on both ports during user-programmed time slots.
Data is always transmitted with the most significant bit first. The output is available every 125 s
and the data is shifted out in 8-bit (16-bit in Linear or PCM Signaling mode) bursts at the PCLK
rate. DXA and DXB are High impedance between time slots, while the device is in the Inactive
mode with no PCM signaling, or while the Cutoff Transmit Path bit (CTP) is on. DXB is not avail-
able on all package types.
Output
GCI Data Upstream. In the GCI mode, the B1, B2, Monitor and SC channel data is serially trans-
mitted on the Data Upstream output for all four channels of the QSLAC device. Which GCI chan-
nels the device uses is determined by the S0 and S1 inputs. Data is always transmitted with the
most significant bit first. 4 bytes of data for each GCI channel is transmitted every 125 s at the
DCL rate.
FS/FSC
Input
Frame Sync. In the PCM/MPI mode, the Frame Sync (FS) pulse is an 8 kHz signal that identifies
Time Slot 0 and Clock Slot 0 of a system’s PCM frame. The QSLAC device references individual
time slots with respect to this input, which must be synchronized to PCLK.
Input
Frame Sync. In GCI mode, the Frame Sync (FSC) pulse is an 8 kHz signal that identifies the be-
ginning of GCI channel 0 of a system’s GCI frame. The QSLAC device references individual GCI
channels with respect to this input, which must be synchronized to DCL.
INT
Output
Interrupt. INT is an active Low output signal, which is programmable as either TTL-compatible or
open drain. The INT output goes Low any time one of the input bits in the Real Time Data register
changes state and is not masked. It also goes Low any time new transmit data appears if this in-
terrupt is armed. INT remains Low until the appropriate register is read via the microprocessor
interface, or the QSLAC device receives either a software or hardware reset. The individual CDxy
bits in the Real Time Data register can be masked from causing an interrupt by using MPI Com-
mand 26 or SOP Command 14. The transmit data interrupt must be armed with a bit in the Oper-
ating Conditions Register.
MCLK/E1
Input/
Output
Master Clock/Enable CD1 Multiplex. In PCM/MPI mode only, the Master Clock can be a 1.536 MHz,
1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor. If the inter-
nal clock is derived from the PCM Clock Input (PCLK) or if GCI mode is selected, this pin can be
used as an E1 output to control AMD SLICs having multiplexed switchhook and ground key detec-
tor outputs.
PCLK/DCL
Input
PCM Clock. In the PCM/MPI mode, the PCM clock determines the rate at which PCM data is se-
rially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency.
The maximum clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for dual
PCM highway versions and 256 kHz for single PCM highway versions. The minimum clock rate
must be doubled if Linear mode or PCM signaling is used. PCLK frequencies between 1.03 MHz
and 1.53 MHz are not allowed. Optionally, the digital signal processor clock can be derived from
PCLK rather than MCLK. In PCM/MPI mode, PCLK can be operated at twice the PCM data rate
in the Double PCLK mode (bit 1 of PCM/MPI Command 45).
Input
GCI Data Clock. In GCI mode, DCL is either 2.048 MHz or 4.096 MHz, which is an integer multiple
of the frame sync frequency. Circuitry internal to the QSLAC device monitors this input to deter-
mine which frequency is being used, 2.048 MHz or 4.096 MHz. When 4.096 MHz clock operation
is detected, internal timing is adjusted so that DU and DD operate at the 2.048 Mbit/s rate.
RST
Input
Reset. A logic Low signal at this pin resets the QSLAC device to its default state.
TSCA, TSCB
Outputs
Time Slot Control. The Time Slot Control outputs are open-drain outputs (requiring pull-up resis-
tors to VDCC) and are normally inactive (high impedance). In the PCM/MPI mode, TSCA or TSCB
is active (low) when PCM data is transmitted on the DXA or DXB pin, respectively. In GCI mode,
TSCA is active (low) during the two GCI time slots selected by the S1 and S0. TSCB is not avail-
able on all package types.
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